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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
Table 19-5. Example of 16-bit EMIFB Address Pin Connections
SDRAM Size Width Banks Address Pins
64M bits ×16 4 SDRAM A[11:0]
EMIFB EMB_A[11:0]
128M bits ×16 4 SDRAM A[11:0]
EMIFB EMB_A[11:0]
19.2.6.3 SDRAM Configuration Registers
The operation of the EMIFB SDRAM interface is controlled by programming the appropriate configuration
registers. This section describes the purpose and function of each configuration register, refer to
Section 19.4 for a more detailed description of each register. The following tables list the SDRAM
configuration registers, along with a description of each of their programmable fields.
NOTE: Writing to any of the fields in SDCFG and SDCFG2 causes the EMIFB to abandon whatever
it is currently doing and trigger the SDRAM initialization procedure described in
Section 19.2.6.4.
Table 19-6. Description of the SDRAM Configuration Register (SDCFG)
Parameter Description
IBANK_POS Internal bank position. Set to 1 to assign internal bank address bits from logical address as shown
in Table 19-16 (this addressing scheme is normally used in case of mobile SDRAM). Clear to 0 to
assign internal bank address bits from logical address as shown in Table 19-14 and Table 19-15
(these addressing schemes are normally used in case of SDR SDRAM) . This bit is writeable only
when the BOOT_UNLOCK bit is unlocked.
MSDRAM_ENABLE mobile SDR enable.Both SDREN and MSDRAM_ENABLE should be set to 1 to enable mobile SDR.
This bit is writeable only when the BOOT_UNLOCK bit is unlocked.
BOOT_UNLOCK Boot Unlock.Set to 1 to change the values of the fields that are affected by the BOOT_UNLOCK bit.
SDREN SDR Enable. This bit enables EMIFB to interface to SDRAM type memories. This bit is set to 1 by
default.
TIMUNLOCK Timing Unlock.Controls the write permission settings for the SDRAM timing 1 register (SDTIM1) and
SDRAM timing 2 register (SDTIM2)
NM Narrow Mode. This bit defines the width of the data bus between the EMIF and the attached SDRAM
device. When set to 1, the data bus is set to 16-bits; when cleared to 0, the data bus is set to 32-bits.
CL CAS latency. This field defines the number of clock cycles between when an SDRAM issues a READ
command and when the first piece of data appears on the bus. The value in this field is sent to the
attached SDRAM device via the LOAD MODE REGISTER command during the SDRAM initialization
procedure as described in Section 19.2.6.4. Only values of 2h (CAS latency = 2) and 3h (CAS latency
= 3) are supported and are written to this field. A 1 must be simultaneously written to the
TIMUNLOCK bit field of SDCFG in order to write to the CL bit field.
EBANK Number of External SDRAM Banks (or chip selects). This field defines the number of chip selects
are utilized on the SDRAM interface:
• When EBANK = 0, CS[0] is used (single external bank). Always write 0 to this field.
IBANK Number of Internal SDRAM Banks. This field defines the number of banks inside the attached
SDRAM devices in the following way:
• When IBANK = 0, 1 internal bank is used
• When IBANK = 1h, 2 internal banks are used
• When IBANK = 2h, 4 internal banks are used
This field value affects the mapping of logical addresses to SDRAM row, column, and bank
addresses. See Section 19.2.6.10 for details.
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