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899
SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
22.2.7 Operating Modes
The I2C peripheral has four basic operating modes to support data transfers as a master and as a slave.
See Table 22-1 for the names and descriptions of the modes.
If the I2C peripheral is a master, it begins as a master-transmitter and, typically, transmits an address for a
particular slave. When giving data to the slave, the I2C peripheral must remain a master-transmitter. In
order to receive data from a slave, the I2C peripheral must be changed to the master-receiver mode.
If the I2C peripheral is a slave, it begins as a slave-receiver and, typically, sends acknowledgment when it
recognizes its slave address from a master. If the master will be sending data to the I2C peripheral, the
peripheral must remain a slave-receiver. If the master has requested data from the I2C peripheral, the
peripheral must be changed to the slave-transmitter mode.
Table 22-1. Operating Modes of the I2C Peripheral
Operating Mode Description
Slave-receiver mode The I2C peripheral is a slave and receives data from a master. All slave modules begin in this
mode. In this mode, serial data bits received on I2Cx_SDA are shifted in with the clock pulses that
are generated by the master. As a slave, the I2C peripheral does not generate the clock signal,
but it can hold I2Cx_SCL low while the intervention of the processor is required (RSFULL = 1 in
ICSTR) after data has been received.
Slave-transmitter mode The I2C peripheral is a slave and transmits data to a master. This mode can only be entered from
the slave-receiver mode; the I2C peripheral must first receive a command from the master. When
you are using any of the 7-bit/10-bit addressing formats, the I2C peripheral enters its slave-
transmitter mode if the slave address is the same as its own address (in ICOAR) and the master
has transmitted R/W = 1. As a slave-transmitter, the I2C peripheral then shifts the serial data out
on I2Cx_SDA with the clock pulses that are generated by the master. While a slave, the I2C
peripheral does not generate the clock signal, but it can hold I2Cx_SCL low while the intervention
of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted.
Master-receiver mode The I2C peripheral is a master and receives data from a slave. This mode can only be entered
from the master-transmitter mode; the I2C peripheral must first transmit a command to the slave.
When you are using any of the 7-bit/10-bit addressing formats, the I2C peripheral enters its
master-receiver mode after transmitting the slave address and R/W = 1. Serial data bits on
I2Cx_SDA are shifted into the I2C peripheral with the clock pulses generated by the I2C
peripheral on I2Cx_SCL. The clock pulses are inhibited and I2Cx_SCL is held low when the
intervention of the processor is required (RSFULL = 1 in ICSTR) after data has been received.
Master-transmitter mode The I2C peripheral is a master and transmits control information and data to a slave. All master
modules begin in this mode. In this mode, data assembled in any of the 7-bit/10-bit addressing
formats is shifted out on I2Cx_SDA. The bit shifting is synchronized with the clock pulses
generated by the I2C peripheral on I2Cx_SCL. The clock pulses are inhibited and I2Cx_SCL is
held low when the intervention of the processor is required (XSMT = 0 in ICSTR) after data has
been transmitted.
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