Texas Instruments TMS320C6745 DSP - ECAP Interrupt Forcing Register (ECFRC); ECAP Interrupt Forcing Register (ECFRC) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Capture (eCAP) Module
13.4.12 ECAP Interrupt Forcing Register (ECFRC)
The ECAP interrupt forcing register (ECFRC) is shown in Figure 13-28 and described in Table 13-25.
Figure 13-28. ECAP Interrupt Forcing Register (ECFRC)
15 14 13 12 11 10 9 8
Reserved
R-0
7 6 5 4 3 2 1 0
CTR=CMP CTR=PRD CTROVF CEVT4 CETV3 CETV2 CETV1 Reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-25. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved
7 CTR=CMP Force Counter Equal Compare Interrupt
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CTR=CMP flag bit.
6 CTR=PRD Force Counter Equal Period Interrupt
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CTR=PRD flag bit.
5 CTROVF Force Counter Overflow
0 No effect. Always reads back a 0.
1 Writing a 1 to this bit sets the CTROVF flag bit.
4 CEVT4 Force Capture Event 4
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT4 flag bit
3 CEVT3 Force Capture Event 3
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT3 flag bit
2 CEVT2 Force Capture Event 2
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT2 flag bit.
1 CEVT1 Force Capture Event 1
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CEVT1 flag bit.
0 Reserved 0 Reserved