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Registers
817
SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.4.6 Performance Counter 1 Register (PC1)
For debug or gathering performance statistics, the PC1 and PC2 counters and associated configuration
registers are provided. These are intended for debug and analysis only. By configuring the performance
counter configuration register (PCC) to define the type of statistics to gather and configuring the
performance counter master region select register (PCMRS) to filter accesses only to specific chip select
regions, performing system applications and then reading these counters, different statistics can be
gathered. To reset the counters, you must reset (SYNC RESET) the EMIFB module through the PSC (for
details on the PSC, see the Power and Sleep Controller (PSC) chapter.
The performance counter 1 register (PC1) is shown in Figure 19-20 and described in Table 19-31.
Figure 19-20. Performance Counter 1 Register (PC1)
31 0
Counter1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-31. Performance Counter 1 Register (PC1) Field Descriptions
Bit Field Value Description
31-0 Counter1 0-FFFF FFFFh 32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register.
19.4.7 Performance Counter 2 Register (PC2)
The performance counter 2 register (PC2) is shown in Figure 19-21 and described in Table 19-32.
Figure 19-21. Performance Counter 2 Register (PC2)
31 0
Counter2
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-32. Performance Counter 2 Register (PC2) Field Descriptions
Bit Field Value Description
31-0 Counter2 0-FFFF FFFFh 32-bit counter that can be configured as specified in the performance counter configuration
register (PCC) and the performance counter master region select register.
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