Texas Instruments TMS320C6745 DSP - USB Clock Multiplexing Options

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SPRUH91D–March 2013–Revised September 2016
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Device Clocking
Table 6-4. USB Clock Multiplexing Options
CFGCHIP2.
USB0PHYCLKMUX
bit
CFGCHIP2.
USB1PHYCLKMUX
bit
USB2.0
Clock
Source
USB1.1
Clock
Source Additional Conditions
0 0 USB_REFCLKIN CLK48MHZ output
from USB2.0 PHY
USB_REFCLKIN must be 12, 24, 48,
19.2, 38.4, 13, 26, 20, or 40 MHz. The
PLL inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies.
0 1 USB_REFCLKIN USB_REFCLKIN USB_REFCLKIN must be 48 MHz. The
PLL inside the USB2.0 PHY can be
configured to accept this input clock
frequency.
1 0 PLL0_AUXCLK CLK48MHZ output
from USB2.0 PHY
PLL0_AUXCLK must be 12, 24, 48, 19.2,
38.4, 13, 26, 20, or 40 MHz. The PLL
inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies.
1 1 PLL0_AUXCLK USB_REFCLKIN PLL0_AUXCLK must be 12, 24, 48, 19.2,
38.4, 13, 26, 20, or 40 MHz. The PLL
inside the USB2.0 PHY can be
configured to accept any of these input
clock frequencies. USB_REFCLKIN must
be 48 MHz.