Texas Instruments TMS320C6745 DSP - External Memory Interface (EMIFA) Registers

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
18.4 Registers
The external memory interface (EMIFA) is controlled by programming its internal memory-mapped
registers (MMRs). Table 18-48 lists the memory-mapped registers for the EMIFA.
NOTE: All EMIFA MMRs, except SDCR, support only word (32-bit) accesses. Performing a byte (8-
bit) or halfword (16-bit) write to these registers results in undefined behavior. The SDCR is
byte writable to allow the setting of the SR, PD and PDWR bits without triggering the
SDRAM initialization sequence.
The EMIFA registers must always be accessed using 32-bit accesses (unless otherwise specified in this
chapter). For the base address of the memory-mapped registers of EMIFA, see your device-specific data
manual.
Table 18-48. External Memory Interface (EMIFA) Registers
Offset Acronym Register Description Section
0h MIDR Module ID Register Section 18.4.1
4h AWCC Asynchronous Wait Cycle Configuration Register Section 18.4.2
8h SDCR SDRAM Configuration Register Section 18.4.3
Ch SDRCR SDRAM Refresh Control Register Section 18.4.4
10h CE2CFG Asynchronous 1 Configuration Register Section 18.4.5
14h CE3CFG Asynchronous 2 Configuration Register Section 18.4.5
18h CE4CFG Asynchronous 3 Configuration Register Section 18.4.5
1Ch CE5CFG Asynchronous 4 Configuration Register Section 18.4.5
20h SDTIMR SDRAM Timing Register Section 18.4.6
3Ch SDSRETR SDRAM Self Refresh Exit Timing Register Section 18.4.7
40h INTRAW EMIFA Interrupt Raw Register Section 18.4.8
44h INTMSK EMIFA Interrupt Mask Register Section 18.4.9
48h INTMSKSET EMIFA Interrupt Mask Set Register Section 18.4.10
4Ch INTMSKCLR EMIFA Interrupt Mask Clear Register Section 18.4.11
60h NANDFCR NAND Flash Control Register Section 18.4.12
64h NANDFSR NAND Flash Status Register Section 18.4.13
70h NANDF1ECC NAND Flash 1 ECC Register (CS2 Space) Section 18.4.14
74h NANDF2ECC NAND Flash 2 ECC Register (CS3 Space) Section 18.4.14
78h NANDF3ECC NAND Flash 3 ECC Register (CS4 Space) Section 18.4.14
7Ch NANDF4ECC NAND Flash 4 ECC Register (CS5 Space) Section 18.4.14
BCh NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register Section 18.4.15
C0h NAND4BITECC1 NAND Flash 4-Bit ECC Register 1 Section 18.4.16
C4h NAND4BITECC2 NAND Flash 4-Bit ECC Register 2 Section 18.4.17
C8h NAND4BITECC3 NAND Flash 4-Bit ECC Register 3 Section 18.4.18
CCh NAND4BITECC4 NAND Flash 4-Bit ECC Register 4 Section 18.4.19
D0h NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1 Section 18.4.20
D4h NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 2 Section 18.4.21
D8h NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1 Section 18.4.22
DCh NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 Section 18.4.23