Texas Instruments TMS320C6745 DSP - Timing Waveform of an Asynchronous Read Cycle in Normal Mode

EMA_CLK
EMA_CS[n]
EMA_WE_DQM
EMA_A/EMA_BA
EMA_D
EMA_OE
EMA_WE
Setup
Strobe
Hold
2
3
2
Address
Data
Byte enable
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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
Table 18-19. Asynchronous Read Operation in Normal Mode (continued)
Time Interval Pin Activity in Normal Mode
Start of the
setup period
The following actions occur at the start of the setup period:
• The setup, strobe, and hold values are set according to the R_SETUP, R_STROBE, and R_HOLD values in
CEnCFG.
• The address pins EMA_A and EMA_BA become valid and carry the values described in Section 18.2.5.1.
• EMA_CS[5:2] falls to enable the external device (if not already low from a previous operation)
Strobe period The following actions occur during the strobe period of a read operation:
1. EMA_OE falls at the start of the strobe period
2. On the rising edge of the clock which is concurrent with the end of the strobe period:
• EMA_OE rises
• The data on the EMA_D bus is sampled by the EMIFA.
In Figure 18-10, EMA_WAIT is inactive. If EMA_WAIT is instead activated, the strobe period can be extended by
the external device to give it more time to provide the data. Section 18.2.5.7 contains more details on using the
EMA_WAIT pin.
End of the hold
period
At the end of the hold period:
• The address pins EMA_A and EMA_BA become invalid
• EMA_CS[5:2] rises (if no more operations are required to complete the current request)
EMIFA may be required to issue additional read operations to a device with a small data bus width in order to
complete an entire word access. In this case, the EMIFA immediately re-enters the setup period to begin another
operation without incurring the turn-round cycle delay. The setup, strobe, and hold values are not updated in this
case. If the entire word access has been completed, the EMIFA returns to its previous state unless another
asynchronous request has been submitted and is currently the highest priority task. If this is the case, the EMIFA
instead enters directly into the turnaround period for the pending read or write operation.
Figure 18-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode