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SYSCFG Registers
201
SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.10.8 Pin Multiplexing Control 7 Register (PINMUX7)
Figure 10-25. Pin Multiplexing Control 7 Register (PINMUX7)
31 28 27 24 23 20 19 16
PINMUX7_31_28 PINMUX7_27_24 PINMUX7_23_20 PINMUX7_19_16
R/W-0 R/W-0 R/W-0 R/W-0
15 12 11 8 7 4 3 0
PINMUX7_15_12 PINMUX7_11_8 PINMUX7_7_4 PINMUX7_3_0
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
(1)
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
(2)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
Table 10-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
Bit Field
ZKB
Ball
(1)
PTP
Pin
(2)
Value Description
31-28 PINMUX7_31_28 N4 9 SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] Control
0 Pin is 3-stated.
1h Selects Function SPI0_SCS[0]
2h Selects Function UART0_RTS
3h Reserved
4h Selects Function EQEP0B
5h-7h Reserved
8h Selects Function GP5[4]
9h-Fh Reserved
27-24 PINMUX7_27_24 R5 12 SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] Control
0 Pin is 3-stated.
1h Selects Function SPI0_ENA
2h Selects Function UART0_CTS
3h Reserved
4h Selects Function EQEP0A
5h-7h Reserved
8h Selects Function GP5[3]
9h-Fh Reserved
23-20 PINMUX7_23_20 T5 11 SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] Control
0 Pin is 3-stated.
1h Selects Function SPI0_CLK
2h Selects Function EQEP1I
3h-7h Reserved
8h Selects Function GP5[2]
9h-Fh Reserved
19-16 PINMUX7_19_16 P6 18 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] Control
0 Pin is 3-stated.
1h Selects Function SPI0_SIMO[0]
2h Selects Function EQEP0S
3h-7h Reserved
8h Selects Function GP5[1]
9h-Fh Reserved