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913
SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
22.3.6 I2C Data Receive Register (ICDRR)
The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive a data
value of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining D
bits are undefined. The number of data bits is selected by the bit count bits (BC) of ICMDR. The I2C
receive shift register (ICRSR) shifts in the received data from the I2Cx_SDA pin. Once data is complete,
the I2C copies the contents of ICRSR into ICDRR. The CPU and the EDMA controller cannot access
ICRSR.
ICDRR is shown in Figure 22-19 and described in Table 22-11.
Figure 22-19. I2C Data Receive Register (ICDRR)
31 16
Reserved
R-0
15 8 7 0
Reserved D
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 22-11. I2C Data Receive Register (ICDRR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 These reserved bit locations are always read as zeros. A value written to this field has no effect.
7-0 D 0-FFh Receive data.
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