Texas Instruments TMS320C6745 DSP - Error Interrupt Command Register (ERRCMD); Error Interrupt Command Register (ERRCMD) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.3.4.5 Error Interrupt Command Register (ERRCMD)
The error interrupt command register (ERRCMD) is shown in Figure 16-89 and described in Table 16-69.
Figure 16-89. Error Interrupt Command Register (ERRCMD)
31 16
Reserved
R-0
15 1 0
Reserved EVAL
R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 16-69. Error Interrupt Command Register (ERRCMD) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 EVAL Error evaluate.
0 No effect.
1 EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set to 1.