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SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Read This First
Preface
SPRUH91D–March 2013–Revised September 2016
Read This First
Code Composer Studio is a trademark of Texas Instruments.
SD is a trademark of SanDisk Corporation.
About This Manual
This Technical Reference Manual (TRM) describes the System-on-Chip (SoC) and each peripheral in the
device. The SoC consists of the following primary components
• DSP subsystem and associated memories
• A set of I/O peripherals
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box provided at www.ti.com.
The current documentation that describes related peripherals and other technical collateral, is available in
the C6000 DSP product folder at: www.ti.com/c6000.
SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors
(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added
functionality and an expanded instruction set.
SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the TMS320C674x
digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain
coherence with external memory, how to use DMA to reduce memory latencies, and how to
optimize your code to improve cache efficiency. The internal memory architecture in the C674x
DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a
dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches
can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
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