Texas Instruments TMS320C6745 DSP - Page 63

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63
SPRUH91D–March 2013–Revised September 2016
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List of Tables
31-82. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions .............................. 1445
31-83. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions .............................. 1446
31-84. Device Control Register (DEVCTL) Field Descriptions............................................................. 1446
31-85. Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions.................................................... 1447
31-86. Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions .................................................... 1447
31-87. Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions ........................................... 1448
31-88. Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions ........................................... 1448
31-89. Hardware Version Register (HWVERS) Field Descriptions........................................................ 1449
31-90. Transmit Function Address (TXFUNCADDR) Field Descriptions................................................. 1450
31-91. Transmit Hub Address (TXHUBADDR) Field Descriptions ........................................................ 1450
31-92. Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................. 1450
31-93. Receive Function Address (RXFUNCADDR) Field Descriptions ................................................. 1451
31-94. Receive Hub Address (RXHUBADDR) Field Descriptions......................................................... 1451
31-95. Receive Hub Port (RXHUBPORT) Field Descriptions.............................................................. 1451
31-96. CDMA Revision Identification Register (DMAREVID) Field Descriptions........................................ 1452
31-97. CDMA Teardown Free Descriptor Queue Control Register (TDFDQ) Field Descriptions ..................... 1452
31-98. CDMA Emulation Control Register (DMAEMU) Field Descriptions............................................... 1453
31-99. CDMA Transmit Channel n Global Configuration Registers (TXGCR[n]) Field Descriptions ................. 1453
31-100. CDMA Receive Channel n Global Configuration Registers (RXGCR[n]) Field Descriptions ................ 1454
31-101. Receive Channel n Host Packet Configuration Registers A (RXHPCRA[n]) Field Descriptions ............ 1455
31-102. Receive Channel n Host Packet Configuration Registers B (RXHPCRB[n]) Field Descriptions ............ 1456
31-103. CDMA Scheduler Control Register (DMA_SCHED_CTRL) Field Descriptions................................ 1457
31-104. CDMA Scheduler Table Word n Registers (WORD[n]) Field Descriptions..................................... 1457
31-105. Queue Manager Revision Identification Register (QMGRREVID) Field Descriptions ........................ 1459
31-106. Queue Manager Queue Diversion Register (DIVERSION) Field Descriptions ................................ 1459
31-107. Queue Manager Free Descriptor/Buffer Starvation Count Register 0 (FDBSC0) Field Descriptions....... 1460
31-108. Queue Manager Free Descriptor/Buffer Starvation Count Register 1 (FDBSC1) Field Descriptions....... 1461
31-109. Queue Manager Free Descriptor/Buffer Starvation Count Register 2 (FDBSC2) Field Descriptions....... 1462
31-110. Queue Manager Free Descriptor/Buffer Starvation Count Register 3 (FDBSC3) Field Descriptions....... 1463
31-111. Queue Manager Linking RAM Region 0 Base Address Register (LRAM0BASE) Field Descriptions ...... 1463
31-112. Queue Manager Linking RAM Region 0 Size Register (LRAM0SIZE) Field Descriptions ................... 1464
31-113. Queue Manager Linking RAM Region 1 Base Address Register (LRAM1BASE) Field Descriptions ...... 1464
31-114. Queue Manager Queue Pending Register 0 (PEND0) Field Descriptions ..................................... 1465
31-115. Queue Manager Queue Pending Register 1 (PEND1) Field Descriptions ..................................... 1465
31-116. Queue Manager Memory Region R Base Address Registers (QMEMRBASE[R]) Field Descriptions ..... 1466
31-117. Queue Manager Memory Region R Control Registers (QMEMRCTRL[R]) Field Descriptions.............. 1467
31-118. Queue Manager Queue N Control Register D (CTRLD[N]) Field Descriptions................................ 1468
31-119. Queue Manager Queue N Status Register A (QSTATA[N]) Field Descriptions ............................... 1469
31-120. Queue Manager Queue N Status Register B (QSTATB[N]) Field Descriptions ............................... 1469
31-121. Queue Manager Queue N Status Register C (QSTATC[N]) Field Descriptions............................... 1470