SYSCFG Registers
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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.18 Chip Configuration 4 Register (CFGCHIP4)
The CFGCHIP4 register is used for clearing the AMUNTEIN signal for the McASPs. Writing a 1 causes a
single pulse that clears the ‘latched’ GPIO interrupt for AMUTEIN of McASP if it was previously set. Reads
always return a value of 0. The register has individual bits for each McASP supported on the device. The
CFGCHIP4 is shown in Figure 10-45 and described in Table 10-49.
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Figure 10-45. Chip Configuration 4 Register (CFGCHIP4)
31 16
Reserved
R-0
15 8 7 3 2 1 0
Reserved Reserved AMUTECLR2
(1)
AMUTECLR1 AMUTECLR0
(1)
R/W-FFh R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15-8 Reserved FFh Reserved. Write the default value when modifying this register.
7-3 Reserved 0 Reserved. Write the default value to all bits when modifying this register.
2 AMUTECLR2 Clears the 'latched' GPIO interrupt for AMUTEIN of McASP2 when set to 1. This peripheral is
not supported on the C6745 DSP.
0 No effect
1 Clears interrupt
1 AMUTECLR1 Clears the 'latched' GPIO interrupt for AMUTEIN of McASP1 when set to 1.
0 No effect
1 Clears interrupt
0 AMUTECLR0 Clears the 'latched' GPIO interrupt for AMUTEIN of McASP0 when set to 1. The AMUTE0
signal is not supported on the C6745 DSP.
0 No effect
1 Clears interrupt
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