PSC Registers
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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0)
The PSC0 module error pending register 0 (MERRPR0) is shown in Figure 8-3 and described in
Table 8-10.
Figure 8-3. PSC0 Module Error Pending Register 0 (MERRPR0)
31 16
Reserved
R-0
15 14 0
M[15] Reserved
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 8-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 M[15] Module interrupt status bit for module 15 (DSP).
0 Module 15 does not have an error condition.
1 Module 15 has an error condition. See the module status 15 register (MDSTAT15) for the error
condition.
14-0 Reserved 0 Reserved
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0)
The PSC1 module error pending register 0 (MERRPR0) is shown in Figure 8-4.
Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0)
31 0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset