Texas Instruments TMS320C6745 DSP - Operation Modes Supported by Raster Controller

MCLK + LCD_CLK when CLKDIV + 0.
MCLK +
LCD_CLK
CLKDIV
when CLKDIV 0 0.
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SPRUH91D–March 2013–Revised September 2016
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Liquid Crystal Display Controller (LCDC)
The timing configuration is based on an internal reference clock, MCLK. The MCLK is generated out of
LCD_CLK, which is determined by the CLKDIV bit in the LCD_CTRL register:
See your device-specific data manual for the timing configurations supported by the LCD controller.
23.2.5 Raster Controller
Raster mode (and the use of this logic) is enabled by setting the MODESEL bit in the LCD control register
(LCD_CTRL). Table 23-4 shows the active external signals when this mode is active.
Table 23-4. Operation Modes Supported by Raster Controller
Interface
Data Bus
Width
Register Bits
RASTER_CTRL[9, 7, 1] Signal Name Description
Passive (STN) Mono
4-bit
4 001 LCD_D[3:0] Data bus
LCD_PCLK Pixel clock
LCD_HSYNC Horizontal clock(Line Clock)
LCD_VSYNC Vertical clock (Frame Clock)
LCD_AC_ENB_CS AC Bias
LCD_MCLK Not used
Passive (STN) Mono
8-bit
8 101 LCD_D[7:0] Data bus
LCD_PCLK Pixel clock
LCD_HSYNC Horizontal clock(Line Clock)
LCD_VSYNC Vertical clock (Frame Clock)
LCD_AC_ENB_CS AC Bias
LCD_MCLK Not used
Passive (STN) Color 8 100 LCD_D[7:0] Data bus
LCD_PCLK Pixel clock
LCD_HSYNC Horizontal clock(Line Clock)
LCD_VSYNC Vertical clock (Frame Clock)
LCD_AC_ENB_CS AC Bias
LCD_MCLK Not used
Active (TFT) Color 16 x10 LCD_D[15:0] Data bus
LCD_PCLK Pixel clock
LCD_HSYNC Horizontal clock(Line Clock)
LCD_VSYNC Vertical clock (Frame Clock)
LCD_AC_ENB_CS Output enable
LCD_MCLK Not used