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PLLC Registers
121
SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4 PLLC Registers
Table 7-2 lists the memory-mapped registers for the PLLC.
(1)
This register is not supported on the C6745 DSP.
Table 7-2. PLL Controller (PLLC) Registers
Address Acronym Register Description Section
01C1 1000h REVID Revision Identification Register Section 7.4.1
01C1 10E4h RSTYPE Reset Type Status Register Section 7.4.2
01C1 1100h PLLCTL PLL Control Register Section 7.4.3
01C1 1104h OCSEL
(1)
OBSCLK Select Register Section 7.4.4
01C1 1110h PLLM PLL Multiplier Control Register Section 7.4.5
01C1 1114h PREDIV PLL Pre-Divider Control Register Section 7.4.6
01C1 1118h PLLDIV1 PLL Controller Divider 1 Register Section 7.4.7
01C1 111Ch PLLDIV2 PLL Controller Divider 2 Register Section 7.4.8
01C1 1120h PLLDIV3 PLL Controller Divider 3 Register Section 7.4.9
01C1 1124h OSCDIV
(1)
Oscillator Divider 1 Register (OBSCLK) Section 7.4.14
01C1 1128h POSTDIV PLL Post-Divider Control Register Section 7.4.15
01C1 1138h PLLCMD PLL Controller Command Register Section 7.4.16
01C1 113Ch PLLSTAT PLL Controller Status Register Section 7.4.17
01C1 1140h ALNCTL PLL Controller Clock Align Control Register Section 7.4.18
01C1 1144h DCHANGE PLLDIV Ratio Change Status Register Section 7.4.19
01C1 1148h CKEN Clock Enable Control Register Section 7.4.20
01C1 114Ch CKSTAT Clock Status Register Section 7.4.21
01C1 1150h SYSTAT SYSCLK Status Register Section 7.4.22
01C1 1160h PLLDIV4 PLL Controller Divider 4 Register Section 7.4.10
01C1 1164h PLLDIV5 PLL Controller Divider 5 Register Section 7.4.11
01C1 1168h PLLDIV6 PLL Controller Divider 6 Register Section 7.4.12
01C1 116Ch PLLDIV7 PLL Controller Divider 7 Register Section 7.4.13
01C1 11F0h EMUCNT0 Emulation Performance Counter 0 Register Section 7.4.23
01C1 11F4h EMUCNT1 Emulation Performance Counter 1 Register Section 7.4.24
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