PLLC Registers
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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4.14 Oscillator Divider 1 Register (OSCDIV)
NOTE: This register is not supported on the C6745 DSP.
The oscillator divider 1 register (OSCDIV) controls the divider for OBSCLK, dividing down the clock
selected as the OBSCLK source from the OBSCLK select register (OCSEL). The OBSCLK is connected
to the OBSCLK pin. The OSCDIV is shown in Figure 7-15 and described in Table 7-16.
Figure 7-15. Oscillator Divider 1 Register (OSCDIV)
31 16
Reserved
R-0
15 14 5 4 0
OD1EN Reserved RATIO
R/W-1 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-16. Oscillator Divider 1 Register (OSCDIV) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 OD1EN Oscillator divider 1 enable.
0 Oscillator divider 1 is disabled.
1 Oscillator divider 1 is enabled. For OBSCLK to toggle, both the OD1EN bit and the OBSEN bit in the
clock enable control register (CKEN) must be set to 1.
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
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