Texas Instruments TMS320C6745 DSP - 14.4.2 Counter-Compare Submodule Registers; Time-Base Period Register (TBPRD); Time-Base Period Register (TBPRD) Field Descriptions

To Next Page

To Previous Page

www.ti.com

Registers

375

SPRUH91D–March 2013–Revised September 2016

Submit Documentation Feedback

Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)

14.4.1.5 Time-Base Period Register (TBPRD)

The time-base period register (TBPRD) is shown in Figure 14-69 and described in Table 14-56.

Figure 14-69. Time-Base Period Register (TBPRD)

15 0

TBPRD

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 14-56. Time-Base Period Register (TBPRD) Field Descriptions

Bits Name Value Description

15-0 TBPRD 0-FFFFh These bits determine the period of the time-base counter. This sets the PWM frequency.

Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is

shadowed.

• If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the

shadow register. In this case, the active register will be loaded from the shadow register when the

time-base counter equals zero.

• If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active

• The active and shadow registers share the same memory map address.

14.4.2 Counter-Compare Submodule Registers

Table 14-57 lists the memory-mapped registers for the counter-compare submodule. See your device-

specific data manual for the memory address of these registers. All other register offset addresses not

listed in Table 14-57 should be considered as reserved locations and the register contents should not be

modified.

(1)

This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this

location is reserved. See your device-specific data manual to determine which instances include the HRPWM.

Related product manuals