Registers
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.3.6.18 Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn)
The destination FIFO memory protection proxy register n (DFMPPRXYn) is shown in Figure 16-108 and
described in Table 16-88.
Figure 16-108. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn)
31 16
Reserved
R-0
15 9 8 7 4 3 0
Reserved PRIV Reserved PRIVID
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-88. Destination FIFO Memory Protection Proxy Register n (DFMPPRXYn)
Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reserved
8 PRIV Privilege level. This contains the privilege level used by the EDMA programmer to set up the parameter
entry in the channel controller. This field is set up when the associated TR is submitted to the
EDMA3TC.
The privilege ID is used while issuing Read and write command to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIV of the host that set up the
DMA transaction.
0 User-level privilege
1 Supervisor-level privilege
7-4 Reserved 0 Reserved
3-0 PRIVID 0-Fh Privilege ID. This contains the Privilege ID of the EDMA programmer that set up the parameter entry in
the channel controller. This field is set up when the associated TR is submitted to the EDMA3TC.
This PRIVID value is used while issuing Read and write commands to the target endpoints so that the
target endpoints can perform memory protection checks based on the PRIVID of the host that set up
the DMA transaction.
0 For any other master that sets up the PaRAM entry
1 If DSP sets up the PaRAM entry
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