Texas Instruments TMS320C6745 DSP - Default Chapter; Table of Contents

2
SPRUH91D–March 2013–Revised September 2016
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Contents
Contents
Preface....................................................................................................................................... 64
1 Overview ........................................................................................................................... 65
1.1 Introduction.................................................................................................................. 66
2 DSP Subsystem ................................................................................................................. 68
2.1 Introduction.................................................................................................................. 69
2.2 TMS320C674x Megamodule ............................................................................................. 70
2.2.1 Internal Memory Controllers ..................................................................................... 70
2.2.2 Internal Peripherals ............................................................................................... 70
2.3 Memory Map................................................................................................................ 74
2.3.1 DSP Internal Memory............................................................................................. 74
2.3.2 External Memory .................................................................................................. 74
2.4 Advanced Event Triggering (AET) ....................................................................................... 75
3 System Interconnect........................................................................................................... 76
3.1 Introduction.................................................................................................................. 77
3.2 System Interconnect Block Diagram..................................................................................... 78
4 System Memory ................................................................................................................. 79
4.1 Introduction.................................................................................................................. 80
4.2 DSP Memories.............................................................................................................. 80
4.3 Peripherals .................................................................................................................. 81
5 Memory Protection Unit (MPU)............................................................................................. 82
5.1 Introduction.................................................................................................................. 83
5.1.1 Purpose of the MPU .............................................................................................. 83
5.1.2 Features ............................................................................................................ 83
5.1.3 Block Diagram ..................................................................................................... 83
5.1.4 MPU Default Configuration....................................................................................... 84
5.2 Architecture ................................................................................................................. 84
5.2.1 Privilege Levels.................................................................................................... 84
5.2.2 Memory Protection Ranges...................................................................................... 85
5.2.3 Permission Structures ............................................................................................ 86
5.2.4 Protection Check .................................................................................................. 87
5.2.5 DSP L1/L2 Cache Controller Accesses ........................................................................ 87
5.2.6 MPU Register Protection......................................................................................... 87
5.2.7 Invalid Accesses and Exceptions ............................................................................... 88
5.2.8 Reset Considerations............................................................................................. 88
5.2.9 Interrupt Support .................................................................................................. 88
5.2.10 Emulation Considerations....................................................................................... 88
5.3 MPU Registers.............................................................................................................. 89
5.3.1 Revision Identification Register (REVID)....................................................................... 91
5.3.2 Configuration Register (CONFIG)............................................................................... 91
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT).............................................................. 92
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT) ........................................................... 93
5.3.5 Interrupt Enable Set Register (IENSET) ....................................................................... 94
5.3.6 Interrupt Enable Clear Register (IENCLR)..................................................................... 94
5.3.7 Fixed Range Start Address Register (FXD_MPSAR) ........................................................ 95