Features
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SPRUH91D–March 2013–Revised September 2016
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Power Management
9.4 Features
This device has several means of managing power consumption, as detailed in the subsequent sections.
This device uses the state-of-the-art 65 nm process, which provides a good balance on power and
performance, providing high-performance transistors with relatively less leakage current and, thereby, low
standby-power consumption modes.
There are several features in design as well as user driven software control to reduce dynamic power
consumption. The design features (not under user control) include a power optimized clock tree design to
reduce overall clock tree power consumption and automatic clock gating in several modules when the
logic in the modules is not active.
The on-chip power and sleep controller (PSC) module provides granular software controlled module level
clock gating, which reduces both clock tree and module power by basically disabling the clocks when the
modules are not being used. Clock management also allows you to slow down the clocks, to reduce the
dynamic power.
Table 9-1 describes the power management features.
(1)
This peripheral is not supported on the C6745 DSP.
Table 9-1. Power Management Features
Power Management Description Features
Clock Management
PLL power-down The PLL can be powered-down and run in bypass
modes when not in use.
Reduces the dynamic power consumption of the
core.
Module clock ON/OFF Module clocks can be turned on/off without
requiring reconfiguring the registers.
Reduces the dynamic/switching power
consumption of the core and I/O (if any free
running I/O clocks).
Core/module clock
frequency scaling
The device can be run at a lower frequency using
the PLLM/PLL dividers. Many modules have
internal clock dividers to scale module/IO
frequency.
Reduces the dynamic/switching power
consumption of core and I/O.
Core Sleep Management
DSP subsystem
sleep mode
The DSP CPU can be put in sleep (IDLE) mode. Reduces the dynamic power.
Voltage Management
RTC-only mode
(1)
Allows removing power from all core and I/O
supply and just have the real-time clock (RTC)
running.
Reduces the dynamic and static power for standby
modes that require only the RTC to be functional.
Peripheral I/O Power Management
USB Phy power-down The USB2.0 Phy can be powered-down. Minimizes USB2.0 I/O power consumption when
not in use.