Texas Instruments TMS320C6745 DSP - Power Error Pending Register (PERRPR); Power Error Clear Register (PERRCR); Power Error Pending Register (PERRPR) Field Descriptions; Power Error Clear Register (PERRCR) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.6.7 Power Error Pending Register (PERRPR)
The power error pending register (PERRPR) is shown in Figure 8-7 and described in Table 8-12.
Figure 8-7. Power Error Pending Register (PERRPR)
31 16
Reserved
R-0
15 2 1 0
Reserved P[1] Rsvd
R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 8-12. Power Error Pending Register (PERRPR) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 P[1] RAM/Pseudo (PD1) power domain interrupt status.
0 RAM/Pseudo power domain does not have an error condition.
1 RAM/Pseudo power domain has an error condition. See the power domain 1 status register (PDSTAT1)
for the error condition.
0 Reserved 0 Reserved
8.6.8 Power Error Clear Register (PERRCR)
The power error clear register (PERRCR) is shown in Figure 8-8 and described in Table 8-13.
Figure 8-8. Power Error Clear Register (PERRCR)
31 16
Reserved
R-0
15 2 1 0
Reserved P[1] Rsvd
R-0 W-0 R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-13. Power Error Clear Register (PERRCR) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 P[1] Clears the interrupt status bit (P) set in the power error pending register (PERRPR) and the interrupt
status bits set in the power domain 1 status register (PDSTAT1).
0 A write of 0 has no effect.
1 A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1.
0 Reserved 0 Reserved