Texas Instruments TMS320C6745 DSP - 32-Bit Timer Unchained Mode Configurations

www.ti.com Introduction
1237
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
64-Bit Timer Plus
28.1.5.4.2.2.3 Enabling the 32-Bit Unchained Mode Timer
The TIM12RS and TIM34RS bits in TGCR determine whether the timer is in reset, or if it is capable of
operating. The TIM12RS bit controls the reset of the timer 1:2 side of the timer and the TIM34RS bit
controls the reset of the timer 3:4 side of the timer. For the timer to operate, the TIM12RS and/or
TIM34RS bits must be set to 1.
The ENAMODEn bit in the timer control register (TCR) controls whether the timer is disabled, enabled to
run once, or enabled to run continuously.
• When the timer is disabled (ENAMODEn = 0), the timer does not run and maintains its current count
value.
• When the timer is enabled for one time operation (ENAMODEn = 1), it counts up until the counter
value equals the period value and then stops.
• When the timer is enabled for continuous operation (ENAMODEn = 2h), the counter counts up until it
reaches the period value, then resets itself to zero and begins counting again.
• When the timer is enabled for continuous operation with period reload (ENAMODEn = 3h), the counter
counts up until it reaches the period value, then resets itself to zero, reloads the period registers
(PRD12 and/or PRD34) with the value in the period reload registers (REL12 and/or REL34), and
begins counting again.
Table 28-4 shows the bit values in TGCR to configure the 32-bit timer in unchained mode.
Once the timer stops, if an external clock is used as the timer clock, the timer must remain disabled for at
least one external clock period or the timer will not start counting again. When using the external clock,
the count value is synchronized to the internal clock.
Note that when both the timer counter and timer period are cleared to 0, the timer can be enabled but the
timer counter does not increment because the timer period is 0.
Table 28-4. 32-Bit Timer Unchained Mode Configurations
32-Bit Timer Configuration
TGCR Bit TCR Bit
TIM12RS TIM34RS ENAMODE12 ENAMODE34
To place the 32-bit timer unchained mode with 4-bit prescaler in
reset
x 0 x 0
To disable the 32-bit timer unchained mode with 4-bit prescaler
(out of reset)
x 1h x 0
To enable the 32-bit timer unchained mode with 4-bit prescaler for
one-time operation
x 1h x 1h
To enable the 32-bit timer unchained mode with 4-bit prescaler for
continuous operation
x 1h x 2h
To enable the 32-bit timer unchained mode with 4-bit prescaler for
continuous operation with period reload
x 1h x 3h
To place the 32-bit timer unchained mode with no prescaler in reset 0 x 0 x
To disable the 32-bit timer unchained mode with no prescaler
(out of reset)
1h x 0 x
To enable the 32-bit timer unchained mode with no prescaler for
one-time operation
1h x 1h x
To enable the 32-bit timer unchained mode with no prescaler for
continuous operation
1h x 2h x
To enable the 32-bit timer unchained mode with no prescaler for
continuous operation with period reload
1h x 3h x