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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
• Error interrupts
For information on the transfer completion interrupts and the error interrupts, see your device-specific data
manual.
16.2.9.1 Transfer Completion Interrupts
The EDMA3CC is responsible for generating transfer completion interrupts to the CPU. The EDMA3
generates a single completion interrupt per shadow region on behalf of all DMA/QDMA channels. Various
control registers and bit fields facilitate EDMA3 interrupt generation.
The transfer completion code (TCC) value is directly mapped to the bits of the interrupt pending register
(IPR), as shown in Table 16-8. For example, if TCC = 00 0000b, IPR[0] is set after transfer completion,
and results in an interrupt generation to the CPU if in the EDMA3CC and device interrupt controller are
configured to allow a CPU interrupt. See Section 16.2.9.1.1 for details on enabling EDMA3 transfer
completion interrupts.
When a completion code is returned (as a result of early or normal completion), the corresponding bit in
IPR is set. For the completion code to be returned, the PaRAM set associated with the transfer must
enable the transfer completion interrupt (final/intermediate) in the channel options parameter (OPT).
The transfer completion code (TCC) can be programmed to any value for a DMA/QDMA channel. There
does not need to be a direct relation between the channel number and the transfer completion code value.
This allows multiple channels having the same transfer completion code value to cause a CPU to execute
the same interrupt service routine (ISR) for different channels.
NOTE: The TCC field in the channel options parameter (OPT) is a 6-bit field and can be
programmed for any value between 0-64. For devices with 32 DMA channels, the TCC
should have a value between 0 to 31 so that it sets the appropriate bits (0 to 31) in IPR (and
can interrupt the CPU(s) on enabling the IER register bits (0-31)).
Table 16-8. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
TCC Bits in OPT
(TCINTEN/ITCINTEN = 1) IPR Bit Set
00 0000b IPR0
00 0001b IPR1
00 0010b IPR2
00 0011b IPR3
00 0100b IPR4
… …
… …
01 1110b IPR30
01 1111b IPR31
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