Texas Instruments TMS320C6745 DSP - Emulation Performance Counter 0 Register (EMUCNT0); Emulation Performance Counter 1 Register (EMUCNT1); Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions; Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions

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7.4.23 Emulation Performance Counter 0 Register (EMUCNT0)
The emulation performance counter 0 register (EMUCNT0) is shown in Figure 7-24 and described in
Table 7-25. EMUCNT0 is for emulation performance profiling. It counts in a divide-by-4 of the system
clock. To start the counter, a write must be made to EMUCNT0. This register is not writable, but only used
to start the register. After the register is started, it can not be stopped except for power on reset. When
EMUCNT0 is read, it snapshots EMUCNT0 and EMUCNT1. The snapshot version is what is read. It is
important to read the EMUCNT0 followed by EMUCNT1 or else the snapshot version may not get updated
correctly.
Figure 7-24. Emulation Performance Counter 0 Register (EMUCNT0)
31 0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-25. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
Bit Field Value Description
31-0 COUNT 0-FFFF FFFFh Counter value for lower 64-bits.
7.4.24 Emulation Performance Counter 1 Register (EMUCNT1)
The emulation performance counter 1 register (EMUCNT1) is shown in Figure 7-25 and described in
Table 7-26. EMUCNT1 is for emulation performance profiling. To start the counter, a write must be made
to EMUCNT0. This register is not writable, but only used to start the register. After the register is started, it
can not be stopped except for power on reset. When EMUCNT0 is read, it snapshots EMUCNT0 and
EMUCNT1. The snapshot version is what is read. It is important to read the EMUCNT0 followed by
EMUCNT1 or else the snapshot version may not get updated correctly.
Figure 7-25. Emulation Performance Counter 1 Register (EMUCNT1)
31 0
COUNT
R-0
LEGEND: R = Read only; -n = value after reset
Table 7-26. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
Bit Field Value Description
31-0 COUNT 0-FFFF FFFFh Counter value for upper 64-bits.