Texas Instruments TMS320C6745 DSP - Performance Counter Configuration Register (PCC); Performance Counter Configuration Register (PCC) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.4.8 Performance Counter Configuration Register (PCC)
The performance counter configuration register (PCC) is shown in Figure 19-22 and described in
Table 19-33.
Table 19-34 shows the possible filter configurations for the two performance counters. These filter
configurations can be used in conjunction with a Master ID and/or an external chip select to obtain
performance statistics for a particular master and/or an external chip select.
Figure 19-22. Performance Counter Configuration Register (PCC)
31 30 29 20 19 16
CNTR2_MSTID_EN CNTR2_REGION_EN Reserved CNTR2_CFG
R/W-0 R/W-0 R-0 R/W-1
15 14 13 4 3 0
CNTR1_MSTID_EN CNTR1_REGION_EN Reserved CNTR1_CFG
R/W-0 R/W-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-33. Performance Counter Configuration Register (PCC) Field Descriptions
Bit Field Value Description
31 CNTR2_MSTID_EN Master ID filter enable for performance counter 2 register (PC2). Refer to Table 19-34 for
details.
0 Master ID filter is disabled. PC2 counts accesses from all masters to SDRAM.
1 Master ID filter is enabled. PC2 counts accesses from the master, corresponding to the
Master ID value in the MST_ID2 bit field of the performance counter master region select
register (PCMRS).
30 CNTR2_REGION_EN Chip select filter enable for performance counter 2 register (PC2). Refer to Table 19-34 for
details.
0 Chip select filter is disabled. PC2 counts total number of accesses (SDRAM + EMIFB
memory-mapped register accesses). The REGION_SEL2 bit field value in the performance
counter master region select register (PCMRS) is a don’t care.
1 Chip select filter is enabled. If the REGION_SEL2 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL2 = 0: PC2 counts accesses to SDRAM memory.
REGION_SEL2 = 7h: PC2 counts accesses to EMIFB memory-mapped registers.
29-20 Reserved 0 Any writes to these bit(s) must always have a value of 0.
19-16 CNTR2_CFG 0-Fh Filter configuration for performance counter 2 register (PC2). Refer to Table 19-34 for
details.
15 CNTR1_MSTID_EN Master ID filter enable for performance counter 1 register (PC1). Refer to Table 19-34 for
details.
0 Master ID filter is disabled. PC1 counts accesses from all masters to SDRAM.
1 Master ID filter is enabled. PC1 counts accesses from the master, corresponding to the
Master ID value in the MST_ID1 bit field of the performance counter master region select
register (PCMRS).
14 CNTR1_REGION_EN Chip select filter enable for performance counter 1 register (PC1). Refer to Table 19-34 for
details.
0 Chip select filter is disabled. PC1 counts total number of accesses (SDRAM + EMIFB
memory-mapped register accesses). The REGION_SEL1 bit field value in the performance
counter master region select register (PCMRS) is a don’t care.
1 Chip select filter is enabled. If the REGION_SEL1 bit field value in the performance counter
master region select register (PCMRS) is:
REGION_SEL1 = 0: PC1 counts accesses to SDRAM memory.
REGION_SEL1 = 7h: PC1 counts accesses to EMIFB memory-mapped registers.
13-4 Reserved 0 Any writes to these bit(s) must always have a value of 0.
3-0 CNTR1_CFG 0-Fh Filter configuration for performance counter 1 register (PC1). Refer to Table 19-34 for
details.