Texas Instruments TMS320C6745 DSP - NAND Flash Write Timing Requirements

W_SETUP ) W_STROBE ) W_HOLD w
t
WC
(m)
t
cyc
* 3
W_HOLD w max
ǒ
t
CLH
(m)
t
cyc
,
t
ALH
(m)
t
cyc
,
t
CH
(m)
t
cyc
,
t
DH
(m)
t
cyc
Ǔ
* 1
W_SETUP + W_STROBE ≥
t
DS
(m)
t
cyc
- 2
W_STROBE w
t
WP
(m)
t
cyc
* 1
W_SETUP w max
ǒ
t
CLS
(m)
t
cyc
,
t
ALS
(m)
t
cyc
,
t
CS
(m)
t
cyc
Ǔ
* 1
Example Configuration www.ti.com
752
SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
To determine the required EMIFA configuration to interface to the NAND Flash for a write operation,
Table 18-43 lists the NAND AC timing parameters for a command latch, address latch, and data input
latch that must be considered.
Table 18-43. NAND Flash Write Timing Requirements
Parameter Description
t
WP
Write Pulse width
t
CLS
CLE Setup time
t
ALS
ALE Setup time
t
CS
CS Setup time
t
DS
Data Setup time
t
CLH
CLE Hold time
t
ALH
ALE Hold time
t
CH
CS Hold time
t
DH
Data Hold time
t
WC
Write Cycle time
Figure 18-28 to Figure 18-30 show the command latch, address latch, and data input latch of the NAND
access.
From Figure 18-28 to Figure 18-30, the following equations may be derived. t
cyc
is the period at which the
EMIFA operates. The W_SETUP, W_STROBE, and W_HOLD fields are programmed in terms of EMIFA
cycles where as the data sheet specifications are typically given is nano seconds. This is explains the
presence of t
cyc
in the denominator of the following equations. A minus 1 is included in the equations
because each field in CEnCFG is programmed in terms of EMIFA clock cycles, minus 1 cycle. For
example, W_SETUP is equal to W_SETUP width in EMIFA clock cycles minus 1 cycle.