Texas Instruments TMS320C6745 DSP - EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)

www.ti.com Registers
627
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
EMAC/MDIO Module
17.3.1.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-
C2TXSTAT)
The EMAC control module interrupt core 0-2 transmit interrupt status register (CnTXSTAT) is shown in
Figure 17-21 and described in Table 17-18
Figure 17-21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register
(CnTXSTAT)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
TXCH7STAT TXCH6STAT TXCH5STAT TXCH4STAT TXCH3STAT TXCH2STAT TXCH1STAT TXCH0STAT
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 17-18. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register
(CnTXSTAT)
Bit Field Value Description
31-8 Reserved 0 Reserved
7 TXCH7STAT Interrupt status for TX Channel 7 masked by the CnTXEN register
0 TX Channel 7 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 7 satisfies conditions to generate a CnTXPULSE interrupt.
6 TXCH6STAT Interrupt status for TX Channel 6 masked by the CnTXEN register
0 TX Channel 6 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 6 satisfies conditions to generate a CnTXPULSE interrupt.
5 TXCH5STAT Interrupt status for TX Channel 5 masked by the CnTXEN register
0 TX Channel 5 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 5 satisfies conditions to generate a CnTXPULSE interrupt.
4 TXCH4STAT Interrupt status for TX Channel 4 masked by the CnTXEN register
0 TX Channel 4 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 4 satisfies conditions to generate a CnTXPULSE interrupt.
3 TXCH3STAT Interrupt status for TX Channel 3 masked by the CnTXEN register
0 TX Channel 3 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 3 satisfies conditions to generate a CnTXPULSE interrupt.
2 TXCH2STAT Interrupt status for TX Channel 2 masked by the CnTXEN register
0 TX Channel 2 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 2 satisfies conditions to generate a CnTXPULSE interrupt.
1 TXCH1STAT Interrupt status for TX Channel 1 masked by the CnTXEN register
0 TX Channel 1 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 1 satisfies conditions to generate a CnTXPULSE interrupt.
0 TXCH0STAT Interrupt status for TX Channel 0 masked by the CnTXEN register
0 TX Channel 0 does not satisfy conditions to generate a CnTXPULSE interrupt.
1 TX Channel 0 satisfies conditions to generate a CnTXPULSE interrupt.