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SYSCFG Registers
203
SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.10.9 Pin Multiplexing Control 8 Register (PINMUX8)
Figure 10-26. Pin Multiplexing Control 8 Register (PINMUX8)
31 28 27 24 23 20 19 16
PINMUX8_31_28 PINMUX8_27_24 PINMUX8_23_20 PINMUX8_19_16
R/W-0 R/W-0 R/W-0 R/W-0
15 12 11 8 7 4 3 0
PINMUX8_15_12 PINMUX8_11_8 PINMUX8_7_4 PINMUX8_3_0
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
(1)
The ZKB ball package is only available on the C6747 DSP; this package is not supported on the C6745 DSP.
(2)
The PTP pin package is only available on the C6745 DSP; this package is not supported on the C6747 DSP.
Table 10-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
Bit Field
ZKB
Ball
(1)
PTP
Pin
(2)
Value Description
31-28 PINMUX8_31_28 R4 7 SPI1_ENA/UART2_RXD/GP5[12] Control
0 Pin is 3-stated.
1h Selects Function SPI1_ENA
2h Selects Function UART2_RXD
3h-7h Reserved
8h Selects Function GP5[12]
9h-Fh Reserved
27-24 PINMUX8_27_24 T4 6 AXR1[11]/GP5[11] Control
0 Pin is 3-stated.
1h Selects Function AXR1[11]
2h-7h Reserved
8h Selects Function GP5[11]
9h-Fh Reserved
23-20 PINMUX8_23_20 N3 4 AXR1[10]/GP5[10] Control
0 Pin is 3-stated.
1h Selects Function AXR1[10]
2h-7h Reserved
8h Selects Function GP5[10]
9h-Fh Reserved
19-16 PINMUX8_19_16 P3 3 UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] Control
0 Pin is 3-stated.
1h Selects Function UART0_TXD
2h Selects Function I2C0_SCL
3h Reserved
4h Selects Function TM64P0_OUT12
5h-7h Reserved
8h Selects Function GP5[9]
9h-Fh Reserved