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SYSCFG Registers
231
SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.15 Chip Configuration 1 Register (CFGCHIP1)
The chip configuration 1 register (CFGCHIP1) controls the following functions:
• eCAP0/1/2 event input source: Allows using McASP TX/RX events or various EMAC TX/RX threshold,
pulse, or miscellaneous interrupt events as eCAP event input sources.
• HPI Control: Allows HPIEN bit control that determines whether or not the HPI module has control over
the HPI pins (multiplexed with other peripheral pins). It also provides configurability to select whether
the host address is a word address or a byte address mode.
• eHRPWM Time Base Clock (TBCLK) Synchronization: Allows the software to globally synchronize all
enabled eHRPWM modules to the time base clock (TBCLK).
• McASP AMUTEIN signal source control: Allows selecting GPIO interrupt from different banks as
source for the McASP AMUTEIN signal. CFGCHIP1 provides this signal source control for all McASPs
on the device.
The CFGCHIP1 is shown in Figure 10-42 and described in Table 10-46.
(1)
This bit is not supported and is Reserved on the C6745 DSP.
Figure 10-42. Chip Configuration 1 Register (CFGCHIP1)
31 27 26 22 21 17 16
CAP2SRC CAP1SRC CAP0SRC HPIBYTEAD
(1)
R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 8
HPIENA
(1)
Reserved TBCLKSYNC AMUTESEL2
(1)
R/W-0 R-0 R/W-0 R/W-0
7 4 3 0
AMUTESEL1 AMUTESEL0
(1)
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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