Texas Instruments TMS320C6745 DSP - Page 15

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15
SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Contents
26.2.5 Interrupt Requests ............................................................................................ 1152
26.2.6 Register Protection Against Spurious Writes .............................................................. 1153
26.2.7 General-Purpose Scratch Registers ........................................................................ 1154
26.2.8 Real-Time Clock Response to Low Power Modes (Idle Configurations) .............................. 1154
26.2.9 Emulation Modes of the Real-Time Clock ................................................................. 1154
26.2.10 Reset Considerations ....................................................................................... 1154
26.3 Registers ................................................................................................................. 1155
26.3.1 Second Register (SECOND)................................................................................. 1156
26.3.2 Minute Register (MINUTE)................................................................................... 1156
26.3.3 Hour Register (HOUR) ....................................................................................... 1157
26.3.4 Day of the Month Register (DAY) ........................................................................... 1158
26.3.5 Month Register (MONTH).................................................................................... 1158
26.3.6 Year Register (YEAR) ........................................................................................ 1159
26.3.7 Day of the Week Register (DOTW)......................................................................... 1159
26.3.8 Alarm Second Register (ALARMSECOND) ............................................................... 1160
26.3.9 Alarm Minute Register (ALARMMINUTE).................................................................. 1160
26.3.10 Alarm Hour Register (ALARMHOUR)..................................................................... 1161
26.3.11 Alarm Day of the Month Register (ALARMDAY) ........................................................ 1162
26.3.12 Alarm Month Register (ALARMMONTH) ................................................................. 1163
26.3.13 Alarm Year Register (ALARMYEAR)...................................................................... 1163
26.3.14 Control Register (CTRL) .................................................................................... 1164
26.3.15 Status Register (STATUS) ................................................................................. 1165
26.3.16 Interrupt Register (INTERRUPT) .......................................................................... 1166
26.3.17 Compensation (LSB) Register (COMPLSB) ............................................................. 1167
26.3.18 Compensation (MSB) Register (COMPMSB)............................................................ 1168
26.3.19 Oscillator Register (OSC)................................................................................... 1169
26.3.20 Scratch Registers (SCRATCH0-SCRATCH2) ........................................................... 1170
26.3.21 Kick Registers (KICK0R, KICK1R) ........................................................................ 1170
27 Serial Peripheral Interface (SPI) ........................................................................................ 1171
27.1 Introduction............................................................................................................... 1172
27.1.1 Purpose of the Peripheral.................................................................................... 1172
27.1.2 Features ........................................................................................................ 1172
27.1.3 Functional Block Diagram.................................................................................... 1173
27.1.4 Industry Standard(s) Compliance Statement .............................................................. 1173
27.2 Architecture .............................................................................................................. 1174
27.2.1 Clock............................................................................................................ 1174
27.2.2 Signal Descriptions............................................................................................ 1174
27.2.3 Operation Modes.............................................................................................. 1174
27.2.4 Programmable Registers..................................................................................... 1175
27.2.5 Master Mode Settings ........................................................................................ 1176
27.2.6 Slave Mode Settings.......................................................................................... 1178
27.2.7 SPI Operation: 3-Pin Mode .................................................................................. 1179
27.2.8 SPI Operation: 4-Pin with Chip Select Mode ............................................................. 1180
27.2.9 SPI Operation: 4-Pin with Enable Mode ................................................................... 1182
27.2.10 SPI Operation: 5-Pin Mode................................................................................. 1184
27.2.11 Data Formats................................................................................................. 1186
27.2.12 Interrupt Support............................................................................................. 1189
27.2.13 DMA Events Support........................................................................................ 1190
27.2.14 Robustness Features ....................................................................................... 1190
27.2.15 Reset Considerations ....................................................................................... 1192
27.2.16 Power Management ......................................................................................... 1192
27.2.17 General-Purpose I/O Pin.................................................................................... 1193
27.2.18 Emulation Considerations .................................................................................. 1193