Texas Instruments TMS320C6745 DSP - Page 14

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14
SPRUH91D–March 2013–Revised September 2016
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Contents
25.2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ........................................... 1102
25.2.6 FIFO Operation During Card Read Operation............................................................. 1103
25.2.7 FIFO Operation During Card Write Operation............................................................. 1105
25.2.8 Reset Considerations......................................................................................... 1105
25.2.9 Initialization..................................................................................................... 1107
25.2.10 Interrupt Support............................................................................................. 1110
25.2.11 DMA Event Support ......................................................................................... 1111
25.2.12 Power Management ......................................................................................... 1111
25.2.13 Emulation Considerations .................................................................................. 1111
25.3 Procedures for Common Operations ................................................................................. 1112
25.3.1 Card Identification Operation ................................................................................ 1112
25.3.2 MMC/SD Mode Single-Block Write Operation Using CPU .............................................. 1115
25.3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA........................................ 1117
25.3.4 MMC/SD Mode Single-Block Read Operation Using the CPU.......................................... 1117
25.3.5 MMC/SD Mode Single-Block Read Operation Using EDMA ............................................ 1119
25.3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU............................................. 1119
25.3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA........................................... 1121
25.3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU ............................................ 1121
25.3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA .......................................... 1123
25.3.10 SDIO Card Function......................................................................................... 1123
25.4 Registers ................................................................................................................. 1124
25.4.1 MMC Control Register (MMCCTL).......................................................................... 1125
25.4.2 MMC Memory Clock Control Register (MMCCLK) ....................................................... 1126
25.4.3 MMC Status Register 0 (MMCST0)......................................................................... 1127
25.4.4 MMC Status Register 1 (MMCST1)......................................................................... 1129
25.4.5 MMC Interrupt Mask Register (MMCIM) ................................................................... 1130
25.4.6 MMC Response Time-Out Register (MMCTOR).......................................................... 1132
25.4.7 MMC Data Read Time-Out Register (MMCTOD)......................................................... 1133
25.4.8 MMC Block Length Register (MMCBLEN)................................................................. 1134
25.4.9 MMC Number of Blocks Register (MMCNBLK) ........................................................... 1135
25.4.10 MMC Number of Blocks Counter Register (MMCNBLC) ............................................... 1135
25.4.11 MMC Data Receive Register (MMCDRR)................................................................ 1136
25.4.12 MMC Data Transmit Register (MMCDXR) ............................................................... 1136
25.4.13 MMC Command Register (MMCCMD) ................................................................... 1137
25.4.14 MMC Argument Register (MMCARGHL) ................................................................. 1139
25.4.15 MMC Response Registers (MMCRSP0-MMCRSP7) ................................................... 1140
25.4.16 MMC Data Response Register (MMCDRSP)............................................................ 1142
25.4.17 MMC Command Index Register (MMCCIDX)............................................................ 1142
25.4.18 SDIO Control Register (SDIOCTL)........................................................................ 1143
25.4.19 SDIO Status Register 0 (SDIOST0)....................................................................... 1144
25.4.20 SDIO Interrupt Enable Register (SDIOIEN) .............................................................. 1145
25.4.21 SDIO Interrupt Status Register (SDIOIST) ............................................................... 1145
25.4.22 MMC FIFO Control Register (MMCFIFOCTL) ........................................................... 1146
26 Real-Time Clock (RTC)..................................................................................................... 1147
26.1 Introduction............................................................................................................... 1148
26.1.1 Purpose of the Peripheral.................................................................................... 1148
26.1.2 Features ........................................................................................................ 1148
26.1.3 Block Diagram ................................................................................................. 1148
26.2 Architecture .............................................................................................................. 1149
26.2.1 Clock Source................................................................................................... 1149
26.2.2 Signal Descriptions............................................................................................ 1149
26.2.3 Isolated Power Supply........................................................................................ 1149
26.2.4 Operation....................................................................................................... 1150