Texas Instruments TMS320C6745 DSP - Page 13

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13
SPRUH91D–March 2013–Revised September 2016
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Contents
24.1.8 Pin Data Clear Register (PDCLR) .......................................................................... 1051
24.1.9 Global Control Register (GBLCTL) ......................................................................... 1053
24.1.10 Audio Mute Control Register (AMUTE) ................................................................... 1055
24.1.11 Digital Loopback Control Register (DLBCTL)............................................................ 1057
24.1.12 Digital Mode Control Register (DITCTL).................................................................. 1058
24.1.13 Receiver Global Control Register (RGBLCTL)........................................................... 1059
24.1.14 Receive Format Unit Bit Mask Register (RMASK) ...................................................... 1060
24.1.15 Receive Bit Stream Format Register (RFMT)............................................................ 1061
24.1.16 Receive Frame Sync Control Register (AFSRCTL)..................................................... 1063
24.1.17 Receive Clock Control Register (ACLKRCTL)........................................................... 1064
24.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL)..................................... 1065
24.1.19 Receive TDM Time Slot Register (RTDM) ............................................................... 1066
24.1.20 Receiver Interrupt Control Register (RINTCTL) ......................................................... 1067
24.1.21 Receiver Status Register (RSTAT)........................................................................ 1068
24.1.22 Current Receive TDM Time Slot Registers (RSLOT)................................................... 1069
24.1.23 Receive Clock Check Control Register (RCLKCHK).................................................... 1070
24.1.24 Receiver DMA Event Control Register (REVTCTL)..................................................... 1071
24.1.25 Transmitter Global Control Register (XGBLCTL)........................................................ 1072
24.1.26 Transmit Format Unit Bit Mask Register (XMASK)...................................................... 1073
24.1.27 Transmit Bit Stream Format Register (XFMT) ........................................................... 1074
24.1.28 Transmit Frame Sync Control Register (AFSXCTL) .................................................... 1076
24.1.29 Transmit Clock Control Register (ACLKXCTL) .......................................................... 1077
24.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) .................................... 1078
24.1.31 Transmit TDM Time Slot Register (XTDM)............................................................... 1079
24.1.32 Transmitter Interrupt Control Register (XINTCTL) ...................................................... 1080
24.1.33 Transmitter Status Register (XSTAT)..................................................................... 1081
24.1.34 Current Transmit TDM Time Slot Register (XSLOT).................................................... 1082
24.1.35 Transmit Clock Check Control Register (XCLKCHK) ................................................... 1083
24.1.36 Transmitter DMA Event Control Register (XEVTCTL).................................................. 1084
24.1.37 Serializer Control Registers (SRCTLn) ................................................................... 1085
24.1.38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5).......................................... 1086
24.1.39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ........................................ 1086
24.1.40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ..................................... 1087
24.1.41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ................................... 1087
24.1.42 Transmit Buffer Registers (XBUFn) ....................................................................... 1088
24.1.43 Receive Buffer Registers (RBUFn)........................................................................ 1088
24.1.44 AFIFO Revision Identification Register (AFIFOREV) ................................................... 1089
24.1.45 Write FIFO Control Register (WFIFOCTL) ............................................................... 1090
24.1.46 Write FIFO Status Register (WFIFOSTS) ................................................................ 1091
24.1.47 Read FIFO Control Register (RFIFOCTL)................................................................ 1092
24.1.48 Read FIFO Status Register (RFIFOSTS)................................................................. 1093
25 Multimedia Card (MMC)/Secure Digital (SD) Card Controller................................................. 1094
25.1 Introduction............................................................................................................... 1095
25.1.1 Purpose of the Peripheral.................................................................................... 1095
25.1.2 Features ........................................................................................................ 1095
25.1.3 Functional Block Diagram.................................................................................... 1095
25.1.4 Supported Use Case Statement ............................................................................ 1095
25.1.5 Industry Standard(s) Compliance Statement .............................................................. 1096
25.2 Architecture .............................................................................................................. 1096
25.2.1 Clock Control .................................................................................................. 1097
25.2.2 Signal Descriptions............................................................................................ 1098
25.2.3 Protocol Descriptions ......................................................................................... 1099
25.2.4 Data Flow in the Input/Output FIFO ........................................................................ 1100