Texas Instruments TMS320C6745 DSP - Page 12

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12
SPRUH91D–March 2013–Revised September 2016
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Contents
22.3.16 I2C Pin Function Register (ICPFUNC) .................................................................... 925
22.3.17 I2C Pin Direction Register (ICPDIR) ....................................................................... 926
22.3.18 I2C Pin Data In Register (ICPDIN) ......................................................................... 927
22.3.19 I2C Pin Data Out Register (ICPDOUT) .................................................................... 928
22.3.20 I2C Pin Data Set Register (ICPDSET) .................................................................... 929
22.3.21 I2C Pin Data Clear Register (ICPDCLR) .................................................................. 930
23 Liquid Crystal Display Controller (LCDC)............................................................................. 931
23.1 Introduction ................................................................................................................ 932
23.1.1 Purpose of the Peripheral ..................................................................................... 932
23.1.2 Features.......................................................................................................... 933
23.1.3 Terminology ..................................................................................................... 933
23.2 Architecture................................................................................................................ 933
23.2.1 Clocking.......................................................................................................... 933
23.2.2 LCD External I/O Signals ...................................................................................... 935
23.2.3 DMA Engine ..................................................................................................... 936
23.2.4 LIDD Controller.................................................................................................. 937
23.2.5 Raster Controller................................................................................................ 939
23.3 Registers................................................................................................................... 949
23.3.1 LCD Revision Identification Register (REVID) .............................................................. 949
23.3.2 LCD Control Register (LCD_CTRL).......................................................................... 950
23.3.3 LCD Status Register (LCD_STAT) ........................................................................... 952
23.3.4 LCD LIDD Control Register (LIDD_CTRL) .................................................................. 955
23.3.5 LCD LIDD CSn Configuration Registers (LIDD_CS0_CONF and LIDD_CS1_CONF)................ 957
23.3.6 LCD LIDD CSn Address Read/Write Registers (LIDD_CS0_ADDR and LIDD_CS1_ADDR)........ 958
23.3.7 LCD LIDD CSn Data Read/Write Registers (LIDD_CS0_DATA and LIDD_CS1_DATA)............. 959
23.3.8 LCD Raster Control Register (RASTER_CTRL)............................................................ 960
23.3.9 LCD Raster Timing Register 0 (RASTER_TIMING_0) .................................................... 967
23.3.10 LCD Raster Timing Register 1 (RASTER_TIMING_1) ................................................... 969
23.3.11 LCD Raster Timing Register 2 (RASTER_TIMING_2) ................................................... 973
23.3.12 LCD Raster Subpanel Display Register (RASTER_SUBPANEL) ...................................... 977
23.3.13 LCD DMA Control Register (LCDDMA_CTRL)............................................................ 979
23.3.14 LCD DMA Frame Buffer n Base Address Registers
(LCDDMA_FB0_BASE and LCDDMA_FB1_BASE) ........................................................ 980
23.3.15 LCD DMA Frame Buffer n Ceiling Address Registers
(LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING) ................................................. 980
24 Multichannel Audio Serial Port (McASP).............................................................................. 981
24.0.16 Features ....................................................................................................... 982
24.0.17 Protocols Supported ......................................................................................... 983
24.0.18 Functional Block Diagram.................................................................................... 984
24.0.19 Definition of Terms ........................................................................................... 992
24.0.20 Overview ....................................................................................................... 995
24.0.21 Clock and Frame Sync Generators ........................................................................ 995
24.0.22 Reset Considerations ....................................................................................... 1035
24.0.23 EDMA Event Support ....................................................................................... 1035
24.0.24 Power Management ......................................................................................... 1035
24.1 Registers ................................................................................................................. 1036
24.1.1 Register Bit Restrictions...................................................................................... 1039
24.1.2 Revision Identification Register (REV) ..................................................................... 1040
24.1.3 Pin Function Register (PFUNC)............................................................................. 1041
24.1.4 Pin Direction Register (PDIR) ............................................................................... 1043
24.1.5 Pin Data Output Register (PDOUT) ........................................................................ 1045
24.1.6 Pin Data Input Register (PDIN).............................................................................. 1047
24.1.7 Pin Data Set Register (PDSET) ............................................................................. 1049