Texas Instruments TMS320C6745 DSP - Page 11

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11
SPRUH91D–March 2013–Revised September 2016
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Contents
21.2.9 Interrupt Support................................................................................................ 879
21.2.10 EDMA Event Support......................................................................................... 880
21.2.11 Power Management .......................................................................................... 880
21.2.12 Emulation Considerations.................................................................................... 881
21.3 Registers................................................................................................................... 881
21.3.1 Revision Identification Register (REVID) .................................................................... 882
21.3.2 Power and Emulation Management Register (PWREMU_MGMT) ...................................... 882
21.3.3 GPIO Enable Register (GPIO_EN) .......................................................................... 883
21.3.4 GPIO Direction 1 Register (GPIO_DIR1).................................................................... 884
21.3.5 GPIO Data 1 Register (GPIO_DAT1) ........................................................................ 884
21.3.6 GPIO Direction 2 Register (GPIO_DIR2).................................................................... 885
21.3.7 GPIO Data 2 Register (GPIO_DAT2) ........................................................................ 886
21.3.8 Host Port Interface Control Register (HPIC) ................................................................ 887
21.3.9 Host Port Interface Write Address Register (HPIAW) ..................................................... 889
21.3.10 Host Port Interface Read Address Register (HPIAR) .................................................... 889
22 Inter-Integrated Circuit (I2C) Module ................................................................................... 890
22.1 Introduction ................................................................................................................ 891
22.1.1 Purpose of the Peripheral ..................................................................................... 891
22.1.2 Features.......................................................................................................... 891
22.1.3 Functional Block Diagram ..................................................................................... 892
22.1.4 Industry Standard(s) Compliance Statement................................................................ 892
22.2 Architecture................................................................................................................ 893
22.2.1 Bus Structure.................................................................................................... 893
22.2.2 Clock Generation ............................................................................................... 894
22.2.3 Clock Synchronization ......................................................................................... 895
22.2.4 Signal Descriptions ............................................................................................. 895
22.2.5 START and STOP Conditions ................................................................................ 896
22.2.6 Serial Data Formats ............................................................................................ 897
22.2.7 Operating Modes ............................................................................................... 899
22.2.8 NACK Bit Generation........................................................................................... 900
22.2.9 Arbitration........................................................................................................ 901
22.2.10 Reset Considerations......................................................................................... 902
22.2.11 Initialization..................................................................................................... 902
22.2.12 Interrupt Support .............................................................................................. 903
22.2.13 DMA Events Generated by the I2C Peripheral............................................................ 904
22.2.14 Power Management .......................................................................................... 904
22.2.15 Emulation Considerations.................................................................................... 904
22.3 Registers................................................................................................................... 905
22.3.1 I2C Own Address Register (ICOAR)......................................................................... 906
22.3.2 I2C Interrupt Mask Register (ICIMR)......................................................................... 907
22.3.3 I2C Interrupt Status Register (ICSTR) ...................................................................... 908
22.3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) ....................................................... 911
22.3.5 I2C Data Count Register (ICCNT)............................................................................ 912
22.3.6 I2C Data Receive Register (ICDRR)......................................................................... 913
22.3.7 I2C Slave Address Register (ICSAR) ........................................................................ 914
22.3.8 I2C Data Transmit Register (ICDXR) ........................................................................ 915
22.3.9 I2C Mode Register (ICMDR) .................................................................................. 916
22.3.10 I2C Interrupt Vector Register (ICIVR) ...................................................................... 920
22.3.11 I2C Extended Mode Register (ICEMDR)................................................................... 921
22.3.12 I2C Prescaler Register (ICPSC)............................................................................. 922
22.3.13 I2C Revision Identification Register (REVID1) ............................................................ 923
22.3.14 I2C Revision Identification Register (REVID2) ........................................................... 923
22.3.15 I2C DMA Control Register (ICDMAC) ...................................................................... 924