Texas Instruments TMS320C6745 DSP - Page 10

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10
SPRUH91D–March 2013–Revised September 2016
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Contents
19.4.10 Interrupt Raw Register (IRR) ................................................................................ 821
19.4.11 Interrupt Mask Register (IMR) ............................................................................... 822
19.4.12 Interrupt Mask Set Register (IMSR) ........................................................................ 823
19.4.13 Interrupt Mask Clear Register (IMCR)...................................................................... 823
20 General-Purpose Input/Output (GPIO) ................................................................................. 824
20.1 Introduction ................................................................................................................ 825
20.1.1 Purpose of the Peripheral ..................................................................................... 825
20.1.2 Features.......................................................................................................... 825
20.1.3 Functional Block Diagram ..................................................................................... 825
20.1.4 Industry Standard(s) Compliance Statement................................................................ 825
20.2 Architecture................................................................................................................ 826
20.2.1 Clock Control.................................................................................................... 826
20.2.2 Signal Descriptions ............................................................................................. 826
20.2.3 Pin Multiplexing ................................................................................................. 826
20.2.4 Endianness Considerations ................................................................................... 826
20.2.5 GPIO Register Structure....................................................................................... 827
20.2.6 Using a GPIO Signal as an Output........................................................................... 830
20.2.7 Using a GPIO Signal as an Input............................................................................. 831
20.2.8 Reset Considerations .......................................................................................... 831
20.2.9 Initialization ...................................................................................................... 832
20.2.10 Interrupt Support .............................................................................................. 832
20.2.11 EDMA Event Support......................................................................................... 833
20.2.12 Power Management .......................................................................................... 833
20.2.13 Emulation Considerations.................................................................................... 833
20.3 Registers................................................................................................................... 834
20.3.1 Revision ID Register (REVID)................................................................................. 835
20.3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN) ...................................................... 836
20.3.3 GPIO Direction Registers (DIRn) ............................................................................. 837
20.3.4 GPIO Output Data Registers (OUT_DATAn) ............................................................... 839
20.3.5 GPIO Set Data Registers (SET_DATAn).................................................................... 841
20.3.6 GPIO Clear Data Registers (CLR_DATAn) ................................................................. 843
20.3.7 GPIO Input Data Registers (IN_DATAn) .................................................................... 845
20.3.8 GPIO Set Rising Edge Interrupt Registers (SET_RIS_TRIGn)........................................... 847
20.3.9 GPIO Clear Rising Edge Interrupt Registers (CLR_RIS_TRIGn) ........................................ 849
20.3.10 GPIO Set Falling Edge Interrupt Registers (SET_FAL_TRIGn) ........................................ 851
20.3.11 GPIO Clear Falling Edge Interrupt Registers (CLR_FAL_TRIGn) ..................................... 853
20.3.12 GPIO Interrupt Status Registers (INTSTATn) ............................................................. 855
21 Host Port Interface (HPI).................................................................................................... 857
21.1 Introduction ................................................................................................................ 858
21.1.1 Purpose of the Peripheral ..................................................................................... 858
21.1.2 Features.......................................................................................................... 858
21.1.3 Functional Block Diagram ..................................................................................... 859
21.1.4 Industry Standard(s) Compliance Statement................................................................ 860
21.1.5 Terminology Used in This Document ........................................................................ 860
21.2 Architecture................................................................................................................ 861
21.2.1 Clock Control.................................................................................................... 861
21.2.2 Memory Map .................................................................................................... 861
21.2.3 Signal Descriptions ............................................................................................. 861
21.2.4 Pin Multiplexing and General-Purpose I/O Control Blocks................................................ 862
21.2.5 Protocol Description ............................................................................................ 863
21.2.6 Operation ........................................................................................................ 863
21.2.7 Reset Considerations .......................................................................................... 878
21.2.8 Initialization ...................................................................................................... 878