Texas Instruments TMS320C6745 DSP - Page 9

www.ti.com
9
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
18.3.1 Hardware Interface ............................................................................................. 736
18.3.2 Software Configuration......................................................................................... 736
18.4 Registers................................................................................................................... 758
18.4.1 Module ID Register (MIDR) ................................................................................... 759
18.4.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 759
18.4.3 SDRAM Configuration Register (SDCR) .................................................................... 761
18.4.4 SDRAM Refresh Control Register (SDRCR)................................................................ 763
18.4.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) .......................................... 764
18.4.6 SDRAM Timing Register (SDTIMR).......................................................................... 766
18.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 767
18.4.8 EMIFA Interrupt Raw Register (INTRAW)................................................................... 768
18.4.9 EMIFA Interrupt Masked Register (INTMSK) ............................................................... 769
18.4.10 EMIFA Interrupt Mask Set Register (INTMSKSET)....................................................... 770
18.4.11 EMIFA Interrupt Mask Clear Register (INTMSKCLR) .................................................... 771
18.4.12 NAND Flash Control Register (NANDFCR) ............................................................... 772
18.4.13 NAND Flash Status Register (NANDFSR)................................................................. 774
18.4.14 NAND Flash n ECC Registers (NANDF1ECC-NANDF4ECC) .......................................... 775
18.4.15 NAND Flash 4-Bit ECC LOAD Register (NAND4BITECCLOAD)....................................... 776
18.4.16 NAND Flash 4-Bit ECC Register 1 (NAND4BITECC1) .................................................. 777
18.4.17 NAND Flash 4-Bit ECC Register 2 (NAND4BITECC2) .................................................. 777
18.4.18 NAND Flash 4-Bit ECC Register 3 (NAND4BITECC3) .................................................. 778
18.4.19 NAND Flash 4-Bit ECC Register 4 (NAND4BITECC4) .................................................. 778
18.4.20 NAND Flash 4-Bit ECC Error Address Register 1 (NANDERRADD1) ................................. 779
18.4.21 NAND Flash 4-Bit ECC Error Address Register 2 (NANDERRADD2) ................................. 779
18.4.22 NAND Flash 4-Bit ECC Error Value Register 1 (NANDERRVAL1)..................................... 780
18.4.23 NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2)..................................... 780
19 External Memory Interface B (EMIFB).................................................................................. 781
19.1 Introduction ................................................................................................................ 782
19.1.1 Purpose of the Peripheral ..................................................................................... 782
19.1.2 Features.......................................................................................................... 782
19.1.3 Functional Block Diagram ..................................................................................... 782
19.2 Architecture................................................................................................................ 783
19.2.1 Clock Control.................................................................................................... 783
19.2.2 EMIF Requests.................................................................................................. 783
19.2.3 Pin Descriptions................................................................................................. 783
19.2.4 Pin Multiplexing ................................................................................................. 784
19.2.5 Memory Map .................................................................................................... 784
19.2.6 SDRAM Controller and Interface ............................................................................. 784
19.2.7 Reset and Initialization Considerations ...................................................................... 802
19.2.8 Interrupt Support................................................................................................ 802
19.2.9 Power Management ............................................................................................ 803
19.2.10 Emulation Considerations.................................................................................... 805
19.3 Example Configuration................................................................................................... 805
19.4 Registers................................................................................................................... 809
19.4.1 SDRAM Configuration Register (SDCFG) .................................................................. 810
19.4.2 SDRAM Refresh Control Register (SDRFC)................................................................ 812
19.4.3 SDRAM Timing 1 Register (SDTIM1)........................................................................ 813
19.4.4 SDRAM Timing 2 Register (SDTIM2)........................................................................ 814
19.4.5 Peripheral Bus Burst Priority Register (BPRIO) ............................................................ 816
19.4.6 Performance Counter 1 Register (PC1) ..................................................................... 817
19.4.7 Performance Counter 2 Register (PC2) ..................................................................... 817
19.4.8 Performance Counter Configuration Register (PCC) ...................................................... 818
19.4.9 Performance Counter Master Region Select Register (PCMRS) ........................................ 820