Texas Instruments TMS320C6745 DSP - Page 8

www.ti.com
8
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
16.6 Setting Up a Transfer .................................................................................................... 569
17 EMAC/MDIO Module.......................................................................................................... 570
17.1 Introduction ................................................................................................................ 571
17.1.1 Purpose of the Peripheral ..................................................................................... 571
17.1.2 Features.......................................................................................................... 571
17.1.3 Functional Block Diagram ..................................................................................... 572
17.1.4 Industry Standard(s) Compliance Statement................................................................ 573
17.1.5 Terminology ..................................................................................................... 573
17.2 Architecture................................................................................................................ 574
17.2.1 Clock Control.................................................................................................... 574
17.2.2 Memory Map .................................................................................................... 575
17.2.3 Signal Descriptions ............................................................................................. 575
17.2.4 Ethernet Protocol Overview ................................................................................... 578
17.2.5 Programming Interface......................................................................................... 579
17.2.6 EMAC Control Module ......................................................................................... 590
17.2.7 MDIO Module ................................................................................................... 591
17.2.8 EMAC Module................................................................................................... 596
17.2.9 MAC Interface................................................................................................... 598
17.2.10 Packet Receive Operation ................................................................................... 602
17.2.11 Packet Transmit Operation .................................................................................. 607
17.2.12 Receive and Transmit Latency .............................................................................. 608
17.2.13 Transfer Node Priority ........................................................................................ 608
17.2.14 Reset Considerations......................................................................................... 609
17.2.15 Initialization..................................................................................................... 610
17.2.16 Interrupt Support .............................................................................................. 612
17.2.17 Power Management .......................................................................................... 616
17.2.18 Emulation Considerations.................................................................................... 616
17.3 Registers................................................................................................................... 617
17.3.1 EMAC Control Module Registers ............................................................................. 617
17.3.2 MDIO Registers................................................................................................. 631
17.3.3 EMAC Module Registers....................................................................................... 644
18 External Memory Interface A (EMIFA).................................................................................. 694
18.1 Introduction ................................................................................................................ 695
18.1.1 Purpose of the Peripheral ..................................................................................... 695
18.1.2 Features.......................................................................................................... 695
18.1.3 Functional Block Diagram ..................................................................................... 695
18.2 Architecture................................................................................................................ 695
18.2.1 Clock Control.................................................................................................... 696
18.2.2 EMIFA Requests................................................................................................ 696
18.2.3 Pin Descriptions................................................................................................. 696
18.2.4 SDRAM Controller and Interface ............................................................................. 698
18.2.5 Asynchronous Controller and Interface ...................................................................... 710
18.2.6 Data Bus Parking ............................................................................................... 729
18.2.7 Reset and Initialization Considerations ...................................................................... 729
18.2.8 Interrupt Support................................................................................................ 730
18.2.9 EDMA Event Support .......................................................................................... 731
18.2.10 Pin Multiplexing................................................................................................ 731
18.2.11 Memory Map................................................................................................... 731
18.2.12 Priority and Arbitration........................................................................................ 732
18.2.13 System Considerations....................................................................................... 733
18.2.14 Power Management .......................................................................................... 734
18.2.15 Emulation Considerations.................................................................................... 735
18.3 Example Configuration................................................................................................... 736