Texas Instruments TMS320C6745 DSP - Page 7

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7
SPRUH91D–March 2013–Revised September 2016
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Contents
15.3.10 eQEP Watchdog Timer Register (QWDTMR)............................................................. 422
15.3.11 eQEP Watchdog Period Register (QWDPRD) ............................................................ 422
15.3.12 QEP Decoder Control Register (QDECCTL) .............................................................. 423
15.3.13 eQEP Control Register (QEPCTL) ......................................................................... 423
15.3.14 eQEP Capture Control Register (QCAPCTL) ............................................................. 426
15.3.15 eQEP Position-Compare Control Register (QPOSCTL) ................................................. 427
15.3.16 eQEP Interrupt Enable Register (QEINT).................................................................. 428
15.3.17 eQEP Interrupt Flag Register (QFLG)...................................................................... 429
15.3.18 eQEP Interrupt Clear Register (QCLR) .................................................................... 430
15.3.19 eQEP Interrupt Force Register (QFRC).................................................................... 432
15.3.20 eQEP Status Register (QEPSTS)........................................................................... 433
15.3.21 eQEP Capture Timer Register (QCTMR) .................................................................. 434
15.3.22 eQEP Capture Period Register (QCPRD) ................................................................. 434
15.3.23 eQEP Capture Timer Latch Register (QCTMRLAT)...................................................... 434
15.3.24 eQEP Capture Period Latch Register (QCPRDLAT)..................................................... 435
15.3.25 eQEP Revision ID Register (REVID) ....................................................................... 435
16 Enhanced Direct Memory Access (EDMA3) Controller........................................................... 436
16.1 Introduction ................................................................................................................ 437
16.1.1 Overview ......................................................................................................... 437
16.1.2 Features.......................................................................................................... 437
16.1.3 Functional Block Diagram ..................................................................................... 439
16.1.4 Terminology Used in This Document ........................................................................ 439
16.2 Architecture................................................................................................................ 441
16.2.1 Functional Overview............................................................................................ 441
16.2.2 Types of EDMA3 Transfers ................................................................................... 444
16.2.3 Parameter RAM (PaRAM)..................................................................................... 447
16.2.4 Initiating a DMA Transfer ...................................................................................... 457
16.2.5 Completion of a DMA Transfer................................................................................ 460
16.2.6 Event, Channel, and PaRAM Mapping ...................................................................... 461
16.2.7 EDMA3 Channel Controller Regions......................................................................... 464
16.2.8 Chaining EDMA3 Channels ................................................................................... 466
16.2.9 EDMA3 Interrupts............................................................................................... 466
16.2.10 Event Queue(s)................................................................................................ 473
16.2.11 EDMA3 Transfer Controller (EDMA3TC)................................................................... 475
16.2.12 Event Dataflow ................................................................................................ 478
16.2.13 EDMA3 Prioritization.......................................................................................... 479
16.2.14 EDMA3CC and EDMA3TC Performance and System Considerations ................................ 481
16.2.15 EDMA3 Operating Frequency (Clock Control) ............................................................ 482
16.2.16 Reset Considerations......................................................................................... 482
16.2.17 Power Management .......................................................................................... 482
16.2.18 Emulation Considerations.................................................................................... 483
16.3 Transfer Examples........................................................................................................ 483
16.3.1 Block Move Example........................................................................................... 483
16.3.2 Subframe Extraction Example ................................................................................ 485
16.3.3 Data Sorting Example.......................................................................................... 486
16.3.4 Peripheral Servicing Example................................................................................. 488
16.4 Registers................................................................................................................... 500
16.4.1 Parameter RAM (PaRAM) Entries............................................................................ 500
16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers........................................................ 507
16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers........................................................ 546
16.5 Tips ......................................................................................................................... 567
16.5.1 Debug Checklist ................................................................................................ 567
16.5.2 Miscellaneous Programming/Debug Tips ................................................................... 568