Texas Instruments TMS320C6745 DSP - Page 6

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6
SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Contents
14.1.2 Submodule Overview .......................................................................................... 283
14.1.3 Register Mapping ............................................................................................... 287
14.2 Architecture................................................................................................................ 288
14.2.1 Overview ......................................................................................................... 288
14.2.2 Proper Interrupt Initialization Procedure ..................................................................... 291
14.2.3 Time-Base (TB) Submodule................................................................................... 292
14.2.4 Counter-Compare (CC) Submodule.......................................................................... 301
14.2.5 Action-Qualifier (AQ) Submodule............................................................................. 306
14.2.6 Dead-Band Generator (DB) Submodule..................................................................... 324
14.2.7 PWM-Chopper (PC) Submodule.............................................................................. 328
14.2.8 Trip-Zone (TZ) Submodule .................................................................................... 332
14.2.9 Event-Trigger (ET) Submodule ............................................................................... 336
14.2.10 High-Resolution PWM (HRPWM) Submodule............................................................. 340
14.3 Applications to Power Topologies ...................................................................................... 347
14.3.1 Overview of Multiple Modules ................................................................................ 347
14.3.2 Key Configuration Capabilities................................................................................ 348
14.3.3 Controlling Multiple Buck Converters With Independent Frequencies................................... 349
14.3.4 Controlling Multiple Buck Converters With Same Frequencies........................................... 352
14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters...................................................... 355
14.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................ 358
14.3.7 Practical Applications Using Phase Control Between PWM Modules ................................... 362
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ...................................................... 363
14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter...................................... 368
14.4 Registers................................................................................................................... 371
14.4.1 Time-Base Submodule Registers ............................................................................ 371
14.4.2 Counter-Compare Submodule Registers.................................................................... 375
14.4.3 Action-Qualifier Submodule Registers ....................................................................... 378
14.4.4 Dead-Band Generator Submodule Registers............................................................... 382
14.4.5 PWM-Chopper Submodule Register ......................................................................... 385
14.4.6 Trip-Zone Submodule Registers.............................................................................. 386
14.4.7 Event-Trigger Submodule Registers ......................................................................... 390
14.4.8 High-Resolution PWM Submodule Registers............................................................... 393
15 Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 396
15.1 Introduction ................................................................................................................ 397
15.2 Architecture................................................................................................................ 400
15.2.1 EQEP Inputs..................................................................................................... 400
15.2.2 Functional Description ......................................................................................... 400
15.2.3 Quadrature Decoder Unit (QDU) ............................................................................. 402
15.2.4 Position Counter and Control Unit (PCCU).................................................................. 405
15.2.5 eQEP Edge Capture Unit...................................................................................... 413
15.2.6 eQEP Watchdog ................................................................................................ 416
15.2.7 Unit Timer Base................................................................................................. 417
15.2.8 eQEP Interrupt Structure ...................................................................................... 417
15.3 eQEP Registers........................................................................................................... 418
15.3.1 eQEP Position Counter Register (QPOSCNT) ............................................................. 419
15.3.2 eQEP Position Counter Initialization Register (QPOSINIT)............................................... 419
15.3.3 eQEP Maximum Position Count Register (QPOSMAX) ................................................... 419
15.3.4 eQEP Position-Compare Register (QPOSCMP) ........................................................... 420
15.3.5 eQEP Index Position Latch Register (QPOSILAT)......................................................... 420
15.3.6 eQEP Strobe Position Latch Register (QPOSSLAT) ...................................................... 420
15.3.7 eQEP Position Counter Latch Register (QPOSLAT)....................................................... 421
15.3.8 eQEP Unit Timer Register (QUTMR) ........................................................................ 421
15.3.9 eQEP Unit Period Register (QUPRD)........................................................................ 421