Texas Instruments TMS320C6745 DSP - Page 5

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5
SPRUH91D–March 2013–Revised September 2016
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Contents
10.5 SYSCFG Registers....................................................................................................... 176
10.5.1 Revision Identification Register (REVID) .................................................................... 177
10.5.2 Device Identification Register 0 (DEVIDR0)................................................................. 177
10.5.3 Boot Configuration Register (BOOTCFG) ................................................................... 178
10.5.4 Silicon Revision Identification Register (CHIPREVID) ..................................................... 178
10.5.5 Kick Registers (KICK0R-KICK1R)............................................................................ 179
10.5.6 Host 1 Configuration Register (HOST1CFG) ............................................................... 180
10.5.7 Interrupt Registers.............................................................................................. 181
10.5.8 Fault Registers .................................................................................................. 184
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)............................................................ 186
10.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) ............................................. 189
10.5.11 Suspend Source Register (SUSPSRC) .................................................................... 226
10.5.12 Chip Signal Register (CHIPSIG) ............................................................................ 228
10.5.13 Chip Signal Clear Register (CHIPSIG_CLR) .............................................................. 229
10.5.14 Chip Configuration 0 Register (CFGCHIP0)............................................................... 230
10.5.15 Chip Configuration 1 Register (CFGCHIP1)............................................................... 231
10.5.16 Chip Configuration 2 Register (CFGCHIP2)............................................................... 235
10.5.17 Chip Configuration 3 Register (CFGCHIP3)............................................................... 237
10.5.18 Chip Configuration 4 Register (CFGCHIP4)............................................................... 238
11 Boot Considerations ......................................................................................................... 239
11.1 Introduction ................................................................................................................ 240
12 Programmable Real-Time Unit Subsystem (PRUSS).............................................................. 241
13 Enhanced Capture (eCAP) Module...................................................................................... 243
13.1 Introduction ................................................................................................................ 244
13.1.1 Purpose of the Peripheral ..................................................................................... 244
13.1.2 Features.......................................................................................................... 244
13.2 Architecture................................................................................................................ 245
13.2.1 Capture and APWM Operating Mode........................................................................ 246
13.2.2 Capture Mode Description..................................................................................... 247
13.3 Applications ............................................................................................................... 254
13.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example ......................................... 255
13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example ........................... 257
13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example ....................................... 259
13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example ......................... 261
13.3.5 Application of the APWM Mode.............................................................................. 263
13.4 Registers................................................................................................................... 270
13.4.1 Time-Stamp Counter Register (TSCTR)..................................................................... 270
13.4.2 Counter Phase Control Register (CTRPHS) ................................................................ 271
13.4.3 Capture 1 Register (CAP1).................................................................................... 271
13.4.4 Capture 2 Register (CAP2).................................................................................... 272
13.4.5 Capture 3 Register (CAP3).................................................................................... 272
13.4.6 Capture 4 Register (CAP4).................................................................................... 273
13.4.7 ECAP Control Register 1 (ECCTL1) ......................................................................... 273
13.4.8 ECAP Control Register 2 (ECCTL2) ......................................................................... 275
13.4.9 ECAP Interrupt Enable Register (ECEINT) ................................................................. 276
13.4.10 ECAP Interrupt Flag Register (ECFLG) .................................................................... 278
13.4.11 ECAP Interrupt Clear Register (ECCLR)................................................................... 279
13.4.12 ECAP Interrupt Forcing Register (ECFRC)................................................................ 280
13.4.13 Revision ID Register (REVID) ............................................................................... 281
14 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)............................................... 282
14.1 Introduction ................................................................................................................ 283
14.1.1 Introduction ...................................................................................................... 283