Texas Instruments TMS320C6745 DSP - Page 4

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4
SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Contents
8.3 Executing State Transitions ............................................................................................. 144
8.3.1 Power Domain State Transitions .............................................................................. 144
8.3.2 Module State Transitions ....................................................................................... 144
8.4 IcePick Emulation Support in the PSC................................................................................. 145
8.5 PSC Interrupts............................................................................................................. 145
8.5.1 Interrupt Events .................................................................................................. 145
8.5.2 Interrupt Registers ............................................................................................... 146
8.5.3 Interrupt Handling................................................................................................ 147
8.6 PSC Registers............................................................................................................. 148
8.6.1 Revision Identification Register (REVID) ..................................................................... 149
8.6.2 Interrupt Evaluation Register (INTEVAL) ..................................................................... 149
8.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) ................................... 150
8.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) ................................... 150
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ...................................... 151
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ...................................... 151
8.6.7 Power Error Pending Register (PERRPR) ................................................................... 152
8.6.8 Power Error Clear Register (PERRCR)....................................................................... 152
8.6.9 Power Domain Transition Command Register (PTCMD)................................................... 153
8.6.10 Power Domain Transition Status Register (PTSTAT)...................................................... 154
8.6.11 Power Domain 0 Status Register (PDSTAT0) .............................................................. 155
8.6.12 Power Domain 1 Status Register (PDSTAT1) .............................................................. 156
8.6.13 Power Domain 0 Control Register (PDCTL0)............................................................... 157
8.6.14 Power Domain 1 Control Register (PDCTL1)............................................................... 158
8.6.15 Power Domain 0 Configuration Register (PDCFG0)....................................................... 159
8.6.16 Power Domain 1 Configuration Register (PDCFG1)....................................................... 160
8.6.17 Module Status n Register (MDSTATn)....................................................................... 161
8.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................ 162
8.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................ 163
9 Power Management........................................................................................................... 164
9.1 Introduction ................................................................................................................ 165
9.2 Power Consumption Overview.......................................................................................... 165
9.3 PSC and PLLC Overview................................................................................................ 165
9.4 Features.................................................................................................................... 166
9.5 Clock Management....................................................................................................... 167
9.5.1 Module Clock ON/OFF.......................................................................................... 167
9.5.2 Module Clock Frequency Scaling.............................................................................. 167
9.5.3 PLL Bypass and Power Down ................................................................................. 167
9.6 DSP Sleep Mode Management......................................................................................... 168
9.6.1 C674x DSP CPU Sleep Mode ................................................................................. 168
9.6.2 C674x Megamodule Sleep Mode.............................................................................. 168
9.7 RTC-Only Mode........................................................................................................... 168
9.8 Additional Peripheral Power Management Considerations.......................................................... 169
9.8.1 USB PHY Power Down Control ............................................................................... 169
9.8.2 EMIFB Memory Clock Gating .................................................................................. 169
10 System Configuration (SYSCFG) Module............................................................................. 170
10.1 Introduction ................................................................................................................ 171
10.2 Protection .................................................................................................................. 172
10.2.1 Requirements to Access SYSCFG Registers............................................................... 173
10.3 Master Priority Control ................................................................................................... 174
10.4 Interrupt Support.......................................................................................................... 175
10.4.1 Interrupt Events and Requests................................................................................ 175
10.4.2 Interrupt Multiplexing ........................................................................................... 175
10.4.3 Host-DSP Communication Interrupts ........................................................................ 175