Texas Instruments TMS320C6745 DSP - Page 438

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
• 32 DMA channels
– Event triggered transfers (transfers initiated by system/peripheral events)
– Manual transfers (CPU(s) initiated DMA transfers)
– Chained transfers (completion of transfer on one channel triggers a transfer on a “chained”
channel)
• 8 QDMA channels
– QDMA channels are triggered automatically upon writing to a parameter RAM (PaRAM) set entry
– Supports linking and chaining features (similar to DMA channels)
– Support for programmable QDMA channel to PaRAM mapping (any PaRAM entry can be used as a
QDMA channel)
– Optimized for use in conjunction to the IDMA controller (internal DMA in DSP subsystem)
• 2 event queues
• 16 event entries per event queue
The EDMA3 transfer controller (EDMA3TC) has the following features:
• Supports 2-dimensional transfers with independent indexes on source and destination (EDMA3CC
manages the 3rd dimension)
• More then one transfer controller allows concurrent transfers
• Programmable priority level for each transfer controller relative to each other and other masters in the
system.
• Support for increment or constant addressing mode transfers
• Error conditions with interrupt support
• Supports more then one in-flight transfer requests
• Debug/status visibility
• 64-bit wide read and write ports
• Little-endian mode
• Transfer controller(s):
– FIFIOSIZE = 128 bytes
– BUSWIDTH (Read/Write Controllers) = 8 byte
– DSTREGDEPTH = 4
– DBS (default) = 16 bytes. The default burst size (DBS) is programmable, and can be configured for
16-, 32-, or 64-bytes burst size. See the Chip Configuration 0 Register (CFGCHIP0) in the System
Configuration (SYSCFG) Module chapter for details to change the default burst size value.