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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
Example 16-4. Command Fragmentation (DBS = 32)
The pseudo code:
1. ACNT = 8, BCNT = 8, SRCBIDX = 8, DSTBIDX = 10, SRCADDR = 64, DSTADDR = 191
Read Controller: This is optimized from a 2D-transfer to a 1D-transfer such that the read side is equivalent
to ACNT = 64, BCNT = 1.
Cmd0 = 32 byte, Cmd0 = 32 byte
Write Controller: Since DSTBIDX != ACNT, it is not optimized.
Cmd0 = 8 byte, Cmd1 = 8 byte, Cmd2 = 8 byte, Cmd3 = 8 byte, Cmd4 = 8 byte, Cmd5 = 8 byte, Cmd6 = 8
byte, Cmd7 = 8 byte.
2. ACNT = 64, BCNT = 1, SRCADDR = 31, DSTADDR = 513
Read Controller: Read address is not aligned.
Cmd0 = 1 byte, (now the SRCADDR is aligned to 32 for the next command)
Cmd1 = 32 bytes
Cmd2 = 31 bytes
Write Controller: The write address is also not aligned.
Cmd0 = 31 bytes, (now the DSTADDR is aligned to 32 for the next command)
Cmd1 = 32 bytes
Cmd2 = 1 byte
16.2.11.1.3 TR Pipelining and Data Ordering
The transfer controller(s) can issue back-to-back transfer requests (TR). The number of outstanding TRs
for a TC is limited by the number of destination FIFO register entries that is controlled by the
DSTREGDEPTH parameter (fixed in design for a given transfer controller). TR pipelining refers to the
ability of the TC read controller to issue read commands for a subsequent TR, while the TC write
controller is still performing writes for the previous TR. Consider the case of 2 TRs (TR0 followed by TR1),
because of TR pipelining, the TC read controller can start issuing the read commands for TR1 as soon as
the last read command for TR0 has been issued, meanwhile the write commands and write data for TR0
are tracked by the destination FIFO registers. In summary, the TC read controller is able to process n TRs
ahead of the write controller, where n is the number of destination FIFO register entries (typically 4).
TR pipelining is useful for maintaining throughput on back-to-back small TRs. It eliminates the read
overhead because reads start in the background of a previous TR writes.
It should be noted that back-to-back TRs are targeted to different end points even though the read return
data for the two TRs might get returned out of order (that is, read data for TR1 might come in before read
data for TR0), the transfer controller issues that the write commands are issued in order (that is, write
commands for TR0 will be issued before write commands for TR1).
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