Toradex Apalis Series - 2.2 PCI Express

Apalis Carrier Board Design Guide
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Figure 3: Pin numbering schema on the bottom side of the module
Figure 4: Pin numbering schema on the module connector land pattern
2.2 PCI Express
The Apalis module form factor only features one PCIe lane as standard interface. Depending on
the module, there may be additional lanes available in the type-specific area.
2.2.1 PCIe Signals
Apalis
Pin
Apalis
Signal Name
I/O
Type
Power
Rail
Description
55
PCIE1_CLK+
O
PCIe
PCIe 100MHz reference clock output positive
53
PCIE1_CLK-
O
PCIe
PCIe 100MHz reference clock output negative
49
PCIE1_TX+
O
PCIe
PCIe transmit data positive
47
PCIE1_TX-
O
PCIe
PCIe transmit data negative
43
PCIE1_RX+
I
PCIe
PCIe receive data positive
41
PCIE1_RX-
I
PCIe
PCIe receive data negative
37
WAKE1_MICO
I
CMOS
3.3V
General purpose wake signal
26
RESET_MOCI#
O
CMOS
3.3V
General reset output of the module
209
I2C1_SDA
I/O
OD
3.3V
I2C interface data, some PICe device need SMB interface for special
configuration
211
I2C1_SCL
O
OD
3.3V
I2C interface clock, some PICe device need SMB interface for special
configuration
Table 3: PCIe signals
The PCIe interface supports polarity inversion. This means that the positive and negative signal pins
can be inverted in order to simplify the layout by avoiding crossing of the signals. Some PCIe
devices support additional lane reversal for multi-lane interfaces. As the standard interfaces on
Apalis provide only a single lane PCIe interface, the lane reversal feature is not relevant to the
Apalis specification. Some Apalis modules provide additional multi-lane PCIe interfaces as type-
specific interfaces. Please consult the datasheets of such modules to determine if lane reversal is
applicable and supported.
Bottom Side
Pin1Pin23
Pin2Pin24
Pin173
Pin164Pin174
Pin321
Pin320
Pin165
Pin17
Pin18
Module Insertion Edge