Toradex Apalis Series - 2.6 Parallel RGB LCD Interface

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com
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Apalis
Pin
Apalis
Signal Name
Recommended Termination
262
USBO1_OC#
Add pull-up resistor or disable the overcurrent function in software
84
USBH_EN
Leave NC if not used
96
USBH_OC#
Add pull-up resistor OR disable the overcurrent function in software
Table 13: Unused USB signal termination
2.6 Parallel RGB LCD Interface
2.6.1 Parallel RGB LCD Signals
Apalis
Pin
Apalis
Signal Name
I/O
Type
Power
Rail
Description
251
LCD1_R0
O
CMOS
3.3V
Red LCD data signals (LSB: 0, MSB: 7)
253
LCD1_R1
O
CMOS
3.3V
255
LCD1_R2
O
CMOS
3.3V
257
LCD1_R3
O
CMOS
3.3V
259
LCD1_R4
O
CMOS
3.3V
261
LCD1_R5
O
CMOS
3.3V
263
LCD1_R6
O
CMOS
3.3V
265
LCD1_R7
O
CMOS
3.3V
269
LCD1_G0
O
CMOS
3.3V
Green LCD data signals (LSB: 0, MSB: 7)
271
LCD1_G1
O
CMOS
3.3V
273
LCD1_G2
O
CMOS
3.3V
275
LCD1_G3
O
CMOS
3.3V
277
LCD1_G4
O
CMOS
3.3V
279
LCD1_G5
O
CMOS
3.3V
281
LCD1_G6
O
CMOS
3.3V
283
LCD1_G7
O
CMOS
3.3V
287
LCD1_B0
O
CMOS
3.3V
Blue LCD data signals (LSB: 0, MSB: 7)
289
LCD1_B1
O
CMOS
3.3V
291
LCD1_B2
O
CMOS
3.3V
293
LCD1_B3
O
CMOS
3.3V
295
LCD1_B4
O
CMOS
3.3V
297
LCD1_B5
O
CMOS
3.3V
299
LCD1_B6
O
CMOS
3.3V
301
LCD1_B7
O
CMOS
3.3V
249
LCD1_DE
O
CMOS
3.3V
Data Enable (other names: Output Enable)
243
LCD1_PCLK
O
CMOS
3.3V
Pixel Clock (other names: Dot Clock, L_PCLK_WR)
247
LCD1_HSYNC
O
CMOS
3.3V
Horizontal Sync (other names: Line Clock, L_LCKL_A0)
245
LCD1_VSYNC
O
CMOS
3.3V
Vertical Sync (other names: Frame Clock, L_FCLK)
239
BKL1_PWM
O
CMOS
3.3V
Backlight PWM, can be used to control the brightness of the LCD
backlight
286
BKL1_ON
O
CMOS
3.3V
Backlight enable signal
205
I2C2_SDA
I/O
OD
3.3V
I
2
C interface that might be used for the extended display identification
data (EDID) or as DDC if a converter to VGA or DVI is added. This
interface is shared with the other display interfaces.
207
I2C2_SCL
O
OD
3.3V
Table 14: Parallel RGB LCD signals