Figure 48: IrDA Reference Schematic
2.15.3 Unused UART Signal Termination
Unused UART interface signals can be left unconnected. For debugging purpose, it is
recommended to have at least the UART1_RXD and UART1_TXD signals available.
2.16 SPI
The serial peripheral interface (SPI) bus is a synchronous, full duplex interface. The Apalis module
form factor features two independent SPI interfaces. Each of these interfaces has one chip select
signal as compatible standard. Some modules may feature an additional chip select signal or
additional SPI interfaces as secondary function of other pins.
The clock polarity and phase of the SPI bus is not standardized. Some peripherals latch the data at
the positive edge of the clock while others latch it at the negative edge. The SPI modes describe
these different behaviors. Make sure that the relevant Apalis module and the peripheral devices
are set to the same SPI mode.
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