Toradex Apalis Series - 5 Appendix A - Physical Pin Definition and Location

Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com
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5 Appendix A – Physical Pin Definition and Location
Signal Group
Module Bottom Side
MXM3 Pins
Module Top Side
Signal Group
GPIO
GPIO1
1
2
PWM1
PWM
GPIO2
3
4
PWM2
GPIO3
5
6
PWM3
GPIO4
7
8
PWM4
GND
9
10
VCC
CAN
GPIO5
11
12
CAN1_RX
GPIO6
13
14
CAN1_TX
GPIO7
15
16
CAN2_RX
GPIO8
17
18
CAN2_TX
SATA
GND
23
24
POWER_ENABLE_MOCI
System Control
SATA1_RX+
25
26
RESET_MOCI#
SATA1_RX-
27
28
RESET_MICO#
GND
29
30
VCC
Gigabit Ethernet
SATA1_TX-
31
32
ETH1_MDI2+
SATA1_TX+
33
34
ETH1_MDI2-
SATA1_ACT#
35
36
VCC
WAKE1_MICO#
37
38
ETH1_MDI3+
PCI-Express
GND
39
40
ETH1_MDI3-
PCIE1_RX-
41
42
ETH1_ACT
PCIE1_RX+
43
44
ETH1_LINK
GND
45
46
ETH1_CTREF
PCIE1_TX-
47
48
ETH1_MDI0-
PCIE1_TX+
49
50
ETH1_MDI0+
GND
51
52
VCC
PCIE1_CLK-
53
54
ETH1_MDI1-
PCIE1_CLK+
55
56
ETH1_MDI1+
Reserved for type-
specific features
GND
57
58
VCC
USB
TS_DIFF1-
59
60
USBO1_VBUS
TS_DIFF1+
61
62
USBO1_SSRX+
TS_1
63
64
USBO1_SSRX-
TS_DIFF2-
65
66
VCC
TS_DIFF2+
67
68
USBO1_SSTX+
GND
69
70
USBO1_SSTX-
TS_DIFF3-
71
72
USBO1_ID
TS_DIFF3+
73
74
USBO1_D+
GND
75
76
USBO1_D-
TS_DIFF4-
77
78
VCC
TS_DIFF4+
79
80
USBH2_D+
GND
81
82
USBH2_D-
TS_DIFF5-
83
84
USBH_EN
TS_DIFF5+
85
86
USBH3_D+
TS_2
87
88
USBH3_D-
TS_DIFF6-
89
90
VCC
TS_DIFF6+
91
92
USBH4_SSRX-
GND
93
94
USBH4_SSRX+
TS_DIFF7-
95
96
USBH_OC#
TS_DIFF7+
97
98
USBH4_D+
TS_3
99
100
USBH4_D-
TS_DIFF8-
101
102
VCC
TS_DIFF8+
103
104
USBH4_SSTX-
GND
105
106
USBH4_SSTX+
TS_DIFF9-
107
108
VCC
UART