2.6.3 Reference Schematics
2.6.3.1 24-bit Display Schematic Example
The parallel RGB interface can cause problems with EMC compliance when used with a high pixel
clock frequency. This can be made worse if a display is connected over flat flex cables. Therefore,
the flat flex cables should be kept as short as possible. Series resistors in the data lines reduce the
slew rate of the signals which instead reduces the radiation problem but can also introduce signal
quality and timing related problems. The serial resistor value is a trade-off between reduction of
electromagnetic radiation and signal quality. A good starting value is 22Ω.
Some displays feature an I
2
C interface for reading out the EDID PROM or additional controls such
as contrast and hue. If the carrier board provides no other display interface with DDC, it is
recommended that the I2C2 on the Apalis module be used for the DDC. If the DDC is used, make
sure that I
2
C device(s) on the RGB display do not interfere with the DDC address 50h. Otherwise,
use a different I
2
C interface on the Apalis module. The I
2
C interfaces on the Apalis module have a
3.3V logic level. If the display requires a 5V interface, add an I
2
C logic level shifter.
Figure 30: 24-bit parallel RGB display reference schematic
To Next Page
Loading...
