2.2.2 Reference Schematics
The PCIe schematic differs depending on whether the PCIe device is soldered directly to the carrier
board (device-down) or is located on a PCIe card. Special care needs to be taken to determine as
to whether or not AC coupling capacitors are required. The maximum trace length of the lanes
depends on whether the design is for an external card or a device-down.
Every PCIe lane consists of a pair of transmitting (TX) and receiving (RX) traces. Unfortunately, the
names RX and TX can be confusing as the host transmitter needs to be connected to the receiver of
the device and vice versa. Normally, the signals are named from the host’s perspective until they
reach the pins of the PCIe device. Therefore, the transmitting pins of the Apalis modules should be
called TX at the carrier board while the receiving pins of the module should be called RX. Please
read carefully the datasheet of the PCIe device in order to make sure that RX and TX are not
inadvertently swapped.
Every PCIe device needs a 100MHz reference clock. It is not permitted to connect a reference clock
to two device loads. The Apalis module provides one reference clock output as a standard
interface. There may be additional PCIe reference clocks outputs in the type-specific area. If there
are not enough PCIe reference clocks available (e.g. if a PCIe switch is used or the PCIe interfaces
in the type-specific area do not provide additional clock outputs), a zero-delay PCIe clock buffer is
required on the baseboard. Some PCIe switches features an internal PCIe clock buffer, which can
avoid the necessity of a dedicated clock buffer.
Figure 5: PCIe reference clock buffer example
2.2.2.1 PCIe x1 Slot Schematic Example
The PCIe card slot design defines that the decoupling capacitors for the TX lanes should be placed
on the module and the RX lanes on the card. Therefore, no additional decoupling capacitors are
permitted to be placed on the carrier board in the RX, TX and reference clock lines.
To Next Page
Loading...
